Abstract
This chapter focuses on a review of state-ofthe- art memory designs and new design methods for near-threshold computing (NTC). In particular, it provides a survey of existing low voltage memory techniques and their pros and cons. It also presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is validated by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-Vt voltage level as the digital logic. Reliability degradation is thus Overcome, which opens the path to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to a view of the future evolution towards 14, 10 and 7 nm technology nodes.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Andersson O et al (2013) Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. In: European solid state circuits conference (ESSCIRC), Bucharest, pp 197–200
Andersson O, Mohammadi B, Meinerzhagen P, Rodrigues JN (2014) A 35fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. In: European solid state circuits conference (ESSCIRC), Venice Lido, pp 243–246
Benini L et al (2005) MPARM: exploring the multi-processor SoC design space with SystemC. J VLSI Sig Proc Syst (41):169–182
Bhavnagarwala A et al (2005) Fluctuation limits & scaling opportunities for CMOS SRAM cells. In: International electron devices meeting (IEDM), Washington, pp 659–662
CACTI 6.0. An integrated cache access time, cycle time, area, leakage, and dynamic power model for uniform and non-uniform cache architectures. http://www.cs.utah.edu/~rajeev/cacti6
Calhoun BH, Chandrakasan A (2006) A 256kb sub-threshold SRAM in 65nm CMOS. In: International solid state circuits conference (ISSCC), San Francisco, pp 2592–2593
Calhoun BH, Chandrakasan AP (2007) A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation. J Solid State Circuits 42:680–688
Calimera A, Macii A, Macii E, Poncino M (2012) Design techniques and architectures for low-leakage SRAMs. In: Transactions on circuits and systems-I (TCAS-I), (59):1992–2007
Chang L et al (2005) Stable SRAM cell design for the 32 nm node and beyond. In: Symposium on VLSI technology, Kyoto, pp 128–129
Chang IJ, Kim J-J, Park SP, Roy K (2008) A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. In: International solid state conference (ISSCC), San Francisco, pp 388–389
Chang M-H, Chiu Y-T, Hwang W (2012) Design and iso-area analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65-nm CMOS. In: Transactions on circuits and systems – II (TCAS-II), (59):429–433
Chang M et al (2013) A sub-0.3V area-efficient L-shaped 7T SRAM with read bitline swing expansion schemes based on boosted read-bitline, asymmetric-VTH read-port, and offset cell VDD biasing techniques. J Solid State Circuits (48):2558–2569
Clerc S et al (2012) A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation soft error tolerance. In: European solid state circuits conference (ESSCIRC), Bordeaux, pp 313–316
Fish R (2012) Future of computers – Part 2: the power wall. EDN network, January 2012
Fujiwara H et al (2008) Quality of a Bit (QoB): a new concept in dependable SRAM. In: International symposium on quality electronic design (ISQED), San Jose, pp 98–102
Fujiwara H et al (2013) A 20nm 0.6V 2.1μW/MHz 128kb SRAM with no half select issue by interleave wordline and hierarchical bitline scheme. In: Symposium VLSI circuits, Kyoto, pp C118–C119
Fukuda T et al (2014) A 7ns-access-time 25uW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current. In: International solid state conference (ISSCC), San Francisco, pp 236–237
Gemmeke T et al. (2013) Cell libraries for robust low-voltage operation in nanometer technologies. J Solid State Electron (84):132–141
Hung LD et al (2007) Utilization of SECDED for soft error and variation-induced defect tolerance in caches. In: Design, automation, and test in Europe conference (DATE), Nice, pp 1–6
Itoh K, Fridi AR, Bellaouar A, Elmasry MI (1996) A deep sub-V, single power-supply SRAM cell with multi-VT, boosted storage node and dynamic load. In: Proceedings of symposium on VLSI circuits, Honolulu, pp 132–133
Khellah M et al (2006) A 4.2GHz 0.3mm2 256kb dual-Vcc SRAM building block in 65 nm CMOS. In: International solid state circuits conference (ISSCC), San Francisco, pp 2572–2581
Kim CH, Kim J-J, Mukhopadhyay S, Roy K (2005) A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans VLSI Syst 13:349–357
Kim T-H, Liu J, Kim CH (2008) A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode. In: Custom integrated circuits conference (CICC), San Jose, pp 407–410
Kim D et al (2011) A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme. In: International symposium on circuits and systems (ISCAS), Rio de Janeiro, pp 69–72
Konijnenburg M et al (2013) Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS. In: International solid state circuits conference (ISSCC), San Francisco, pp 430–431
Kulkarni JP, Kim K, Roy K (2007) A 160 mV, Fully Differential, Robust Schmitt Trigger Based Sub-threshold SRAM. In: Int. Symp. on Low Power Electronics and Design (ISLPED), pp. 171–176
Kulkarni JP, Kim K, Park SP, Roy K (2008) Process variation tolerant SRAM array for ultra low voltage applications. In: Design automation conference (DAC), Anaheim, pp 108–113
Lohstroh J, Seevinck E, Groot J (1983) Worst-case static noise margin criteria for logic circuits and their mathematical equivalence. J Solid State Circuits (18):803–806
Maeda N et al (2013) A 0.41 μA standby leakage 32 kb embedded SRAM with low-voltage resume-standby utilizing all digital current comparator in 28 nm HKMG CMOS. J Solid State Circuits (48):917–923
Meenderinck C, Juurlink B (2008) (When) Will CMPs hit the power wall? In: Proceedings of EuroPar conference, Las Palmas, Spain, LNCS, vol 5415, pp 184–193
Meinerzhagen P et al (2012) A 500 fW/bit 14 fJ/bit-access 4kb standard cell based sub-VT memory in 65nm CMOS. In: European solid state circuits conference (ESSCIRC), Bordeaux, pp 321–324
Miyaji K et al (2011) Improvement of read margin and its distribution by Vth mismatch self-repair in 6T-SRAM with asymmetric pass gate transistor formed by post-process local electron injection. J Solid State Circuits (46):2180–2188
Morita Y et al (2007) An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment. In: Proceedings of IEEE symposium on VLSI circuits, Kyoto, pp 256–257
Nakagome Y, Horiguchi M, Kawahara T, Itoh K (2003) Review and future prospects of low-voltage RAM circuits. IBM J Res Dev (47):525–552
Nii K et al (2004) A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. J Solid State Circuits 39:684–693
Nii K et al (2007) A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. In: International solid state circuits conference (ISSCC), San Francisco, pp 326–327
Nii K et al (2013) A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. In: International symposium on quality electronic design (ISQED), Santa Clara, pp 438–441
NXP. NXP ARM-based microntrollers. www.nxp.com/documents/datasheet/LH7A400N.pdf
Ohbayashi S et al (2007) A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. J Solid State Circuits 42:820–829
Pilo H et al (2007) An SRAM design in 65-nm technology node featuring read and write-assist circuits to expand operating voltage. J Solid State Circuits 42:813–819
Qazi M, Sinangil ME, Chandrakasan AP (2011) Challenges and directions for low-voltage SRAM. In: IEEE design & test of computers, (28):32–43
Qin H et al (2004) SRAM leakage suppression by minimizing standby supply voltage. In: International symposium on quality electronic design (ISQED), San Jose, pp 55–60
Qin H et al (2008) Error-tolerant SRAM design for ultra-low power standby operation. International symposium on quality electronic design (ISQED), San Jose, pp 30–34
Raghavan P et al (2015) Holistic device exploration for 7nm node. In: Custom integrated circuits conference (CICC) San Jose, pp 16.1.1–16.1.4
Rooseleer B, Dehaene W (2013) A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump. In: European solid state circuits conference (ESSCIRC), pp 201–204
Rooseleer B, Cosemans S, Dehaene W (2011) A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link. In: European solid state circuits conference (ESSCIRC), Bucharest, Helsinki, pp 519–522
Sabry MM et al (2012) A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems. In: Design, automation, and test in europe conference (DATE), Dresden, pp 1110–1113
Sabry MM et al (2014) OCEAN: an optimized HW/SW reliability mitigation approach for scratchpad memories in real-time SoCs. ACM TECS (13): art. 138
Seongmoo H, Barr K, Hampton M, Asanovic K (2002) Dynamic fine-grain leakage reduction using leakage-biased bitlines. In: International symposium on computer arithmetic (ISCA), Anchorage, pp 137–147
Sil A, Ghosh S, Bayoumi M (2007) A novel 90nm 8T SRAM cell with enhanced stability. In: International conference integrated circuit design and technology (ICICDT), Austin, pp 1–4
Sinangil ME, Verma N, Chandrakasan AP (2008) A reconfigurable 65nm SRAM achieving voltage scalability from 0.25–1.2V and performance scalability from 20kHz–200MHz. In: European solid state circuits conference (ESSCIRC), Edinburgh, pp 282–285
Takeda K et al (2006) A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. J Solid State Circuits (41):113–121
Takeyama Y et al (2006) A low leakage SRAM macro with replica cell biasing scheme. J Solid State Circuits (41):815–822
Theon A et al (2013) Impact of multi-gate device architectures on digital and analog circuits and its implications on system-on-chip technologies. In: International electron devices meeting (IEDM) Washington, pp 17.3.1–17.3.3
Verma N, Chandrakasan A (2007)A 65nm 8T Sub-Vt SRAM employing sense-amplifier redundancy. In: International solid state circuits conference (ISSCC), San Francisco, pp 328–329
Wang J, Calhoun BH (2008) Techniques to extend canary-based standby VDD scaling for SRAMs to 45 nm and beyond. J Solid State Circuits (45):2514–2523
Wang A, Chandrakasan A (2005) A 180-mV subthreshold FFT processor using a minimum energy design methodology. J Solid State Circuits (40):310–319
Wang Y et al (2008) A 1.1 GHz 12 μA/Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications. J Solid State Circuits (43):172–179
Wang Z et al (2010) Design of memories with concurrent error detection and correction by nonlinear SEC-DED codes. J Electr Test (26):559–580
Wilton SJE, Jouppi NP (1996) CACTI: an enhanced cache access and cycle time model. J Solid State Circuits (31):677–688
Yabuuchi M et al (2009) A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist. In: Proceedings of symposium on VLSI circuits, Kyoto, pp 158–159
Yamaoka M et al (2004) A 300 MHz 25mA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. In: International solid state circuits conference (ISSCC), San Francisco, pp 494–495, 542
Yamaoka M et al (2008) 65nm low-power high-density SRAM operable at 1.0V under 3s systematic variation using separate Vth monitoring and body bias for NMOS and PMOS. In: International solid state circuits conference (ISSCC), San Francisco, pp 384–385, 622
Yang W-B, Wang C-H, Chuo I-T, Hsu H-H (2012) A 300mV 10MHz 4kb 10T subthreshold SRAM for ultralow-power application. In: International symposium on intelligent signal processing and communication systems (ISPACS), New Taipei City, pp 604–608
Ye Y, Khellah M, Somasekhar D, Farhang A, De V (2003) A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. J Solid State Circuits 38:839–842
Yokoyama Y et al (2014) 40nm ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU. In: International symposium on quality electronic design (ISQED), Santa Clara, 2014, pp 24–31
Zhai B et al (2008) A variation-tolerant sub-200mV 6-T subthreshold SRAM. J Solid State Circuits (43):2338–2348
Zhang K et al (2006) A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. J Solid State Circuits (41):146–151
Acknowledgments
This work was partially supported by the EU FP7 Project Phidias (GA n. 318013) and IMEC’s IIAP program.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Gemmeke, T., Sabry, M.M., Stuijt, J., Schuddinck, P., Raghavan, P., Catthoor, F. (2016). Memories for NTC. In: Hübner, M., Silvano, C. (eds) Near Threshold Computing. Springer, Cham. https://doi.org/10.1007/978-3-319-23389-5_5
Download citation
DOI: https://doi.org/10.1007/978-3-319-23389-5_5
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-23388-8
Online ISBN: 978-3-319-23389-5
eBook Packages: EngineeringEngineering (R0)