Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies

Abstract

In this paper, We propose a faster algorithm for the following instruction scheduling problem: Given a set of UET (Unit Execution Time) instructions with precedence constraints in the form of a DAG (Directed Acyclic Graph), latency constraints where latencies between any two instructions are restricted to be either 0 or 1, timing constraints in the form of individual integer release times and deadlines and a single RISC processor, find a feasible schedule which satisfies all constraints. The time complexity of our algorithm is O(n ² log n) + min{O(ne), O(n ^2.376)}, where n is the number of instructions and e is the number of edges in the precedence graph. Our algorithm is faster than the existing algorithm which runs in O(n ³α(n)) time, where α(n) is the inverse of Ackermann function. In addition, our algorithm can be used to solve the maximum lateness minimization problem in O(n ²log² n + min{ne, n ^2.376}) time.