Traveling the Wild Frontier of Ultra Low-Power Design

Abstract

Power concerns have been at the forefront for the last decade, yet were always considered a second order citizen with respect to other design metrics. Today however, few will dispute that CMOS has entered the “power-limited scaling regime,” with power dissipation becoming the limiting factor on what can be integrated on a chip and how fast it can run. Many approaches have been proposed over to address the concerns regarding both active and standby power. Yet, none of these provides a persistent answer enabling technology scaling may go on in the foreseeable future. Fortunately, a number of researchers are currently engaging in ultra-low power design (ULP), providing a glimpse on potential innovative solutions as well as clear showstoppers. In this talk, we first will present a perspective on power roadmaps and challenges. The second part of the presentation will present some of the solutions currently being considered in the ULP community. The talk will conclude with some long-term perspectives.