Abstract
The mechanisms of delay time generation in graded gate field-plate (FP) AlGaN/GaN high electron mobility transistors (HEMTs) are investigated using Monte Carlo simulation. The graded gate FP suppresses the increase in the maximum electric field with the drain voltage by extending the high electric field area toward the drain. However, in addition to the FP capacitance delay time caused by the capacitance between the FP and the channel, the extension of the high electric field area itself increases the electron accumulation delay time caused by electron occupation of the upper valleys. Eventually, as the FP angle increases, the intrinsic cutoff frequency fT decreases.