In this thesis, the concepts of setting AI motor speed track and motion control card technology are combined. The hardware/software co-designed method is applied to design a stepping motor controller and implement it on the FPGA chip. There are three main parts: (1) RS-232 communication module, (2) NIOS II master, and (3) motor controller. In the RS-232 communication module, the packet receive format by Verilog Hardware Description Language (HDL) is designed. The control commands are sent to the NIOS II master through Avalon Bus. In the NIOS II master, the acceleration, maximum speed, deceleration, and three speed execution time are calculated by control commands. The calculation results are sent to the motor controller through Avalon Bus. In the motor controller, the functional design of motion control card is reference to design various functional modules. Each module is mounted to the Avalon Bus, they are free to be mounted or removed in the future. The experimental results illustrate that the motor can be normal operation in any speed. Moreover, the proposed architecture and design can let the inexperienced users operate it easily.