The semiconductor technology has been advanced in modern VLSI design. Three-dimension (3D) concept imports an additional dimension for circuit design by using stack structures with through-silicon via (TSV). 3D ICs replace longer interconnect in 2D ICs with TSV cells. However, there are problems how to place cells and TSV cells to improve timing. In this thesis, we perform standard cell placement by min-cut partitioning for one layer after layer assignment and address alignment constraint at the same time. Then use simulated-annealing to optimize timing and reduces wirelength of interconnect. In the last, a legal placement by a greedy method removes operlap between cells and TSV cells. The experimental results show that 3D ICs improve wirelength and delay of critical path than 2D ICs.