Nowadays, FinFET is one of the most promising vertical channel structures while the technology node extends to 16 nm. Comparing with the low power (LP; threshold voltage (Vth) equals to 260 mV) devices that the channel doping is not smaller than 1.5x1018 cm-3 called the heavily doped channel, the lightly doped channel which is not larger than 1017 cm-3 for the high speed (HS; Vth equals to 140 mV) devices provide a new technique evaluation to reduce the intrinsic fluctuation. To narrow the power consumption on the LP and HS devices, scaling down the applied voltage (VDD; from 0.6 V to 0.8 V) is the trend of the next-generation. Therefore, for the devices with different Vth and VDD, the fluctuation of devices characteristics has been one of the urgent issues to study. For the sub-16 nm LP and HS high-k/metal gate (HKMG) bulk FinFET devices with VDD equaling to 0.6 V and 0.8 V, in this thesis, we use 3D experimentally calibrated device and circuit simulation to investigate the intrinsic fluctuations of studied devices including the random dopant fluctuation (RDF), random workfunction fluctuation (WKF), and interface trap fluctuation (ITF). We focus on not only the device's DC/AC characteristics, but also the characteristics in digital circuit, such as the power consumption, DC transfer properties, associated timing parameters, and noise margin (NM). From simulation results of statistically numerous samples, under the DC bias, statistical sum of Vth with respect to each associated fluctuation sources (SUM = (Vth,RDs+Vth,WKs+Vth,ITs)0.5) has been overestimated compared with the devices' fluctuation suffering from fluctuation sources simultaneously (ALL; consider RDF, WKF, and ITF concurrently). Since the drain bias of DC (VD = VDD) is larger than that of AC (VD = 0.05 V), near the drain side, the fluctuated potential is more significant in AC condition. As a result, SUM of maximum gate capacitance (Cg, max) has been underestimated compared with ALL of it. Besides, for the HS devices, both of the intrinsic parameters in DC and Cg, max in AC would be improved due to the elimination of RDF. As for the inverter circuits composed of aforementioned LP and HS devices with different VDD, due to association between NM and device's Vth, the trend of fluctuations of NM is the same as that of the Vth for the device in DC condition: ALL > RDF > WKF > ITF. Falling time (tf; the time required for the output voltage (Vout) to fall from 90% of thelogic“1” level to 10% of the logic “1” level.)/raising time (tr; the time required for the Vout to rise from 10% of thelogic“1” level to 90% of the logic “1” level.) is corresponding to the capability of discharging/charging of n-/p-type devices for the timing parameters of aforesaid inverter circuits. Also, the fluctuation trend of tf, tr, and average propagation delay time is the same as the NM's. However, while VDD equals to 0.8 V, the fluctuation of each term (i.e., ALL, RDF, WKF, and ITF) for the Vout at 90% of the logic “1” level is almost the same. As a consequence, the fluctuation of tr is: ALL > ITF > WKF > RDF in sequence. The fluctuations of timing parameters are larger than 5 % because of the poor capability of charging and discharging due to the low VDD equaling to 0.6 V and high Vth. The relative equations about power consumption in inverter circuit: (static power consumption) , (dynamic power consumption) , and (short circuit power consumption) imply that power consumption is governed by VDD. Since the relationship between leakage current and Vth is exponential decay, the increasing Vth results in dramatically reducing leakage current, where the change of ratio on static power consumption of LP as well as HS circuits with same VDD follows the change of ratio on leakage current of that. Notably, for the before-mentioned inverter circuits, in addition to the severe fluctuation for the normalized standard variation of static power consumption, other power consumption terms have been suppressed below 5%. Owing to the elimination of RDF, the power consumption in the HS inverter circuit has been lightly improved compared with that in the LP inverter circuit. In this thesis, we have successfully investigated the impact of intrinsic parameters fluctuation on characteristic variability of sub-16-nm LP as well as HS HKMG bulk FinFET device and circuit with VDD = 0.6 and 0.8 V. The main findings of this research are useful for developing advanced fabrication and device technologies in semiconductor industry.