Through the advance of IC design, how to minimize the power consumption has become a very important issue. Clock gating technique has been used widely in high performance VLSI design to reduce clock network power consumption. We can reduce power consumption by shutting off part of clock gating cells during the idle state. In addition, using clock gate technique also can reduce the overall chip size. Because of the progress of IC manufacturing, buffers and clock gates have different input capacitances in different manufacturing process. Therefore, in this paper, we propose an approach to solve the aforementioned problem. By using flip-flop clustering and merging clock gates, we can construct a gated clock tree which satisfies the setup time constraint. In addition, according to the fan-out number of a clock gating cell, we derive a parameter γ that can be used to adjust the tradeoff between clock gating cells and buffers. The experimental results show that our proposed approach can adjust the tradeoff between clock gate and buffer efficiently by different manufacturing process parameters. Moreover, compared with greedy algorithm result, our proposed approach reduces 87% of the cost function on the average.