並列摘要
Square circuit (or squarer) is widely used in wireless communication systems and electronic measurement equipments. In this thesis, based on a novel square algorithm, a new all-digital squarer is designed and implemented. The new squarer not only has a faster operation speed and but also saves the chip area. To validate the performance of the squarer, the Altera FPGA platform and Verilog are used to realize the squarer and simulate its speed. Compared to existing squarer based on Booth algorithm, the new squarer can achieve as much as a 10% ~20% higher speed depending on the total bits used to represent the input.
參考文獻
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