Brain-inspired computing aims to mimic the computing methodology of the human brain in computers or silicon chips in order to achieve human-level intelligence and efficiency, and thus support a wide range of intelligent processing. Hierarchical Temporal Memory (HTM) is a brain-inspired machine learning algorithm that mimics the structure and operation of human neocortex. In this thesis, we apply the HTM algorithm to visual recognition problems, and show that HTM is robust to noise and distortion in the input. We propose an ASIC implementation of HTM processor with high efficiency and scalability, suitable for real-time and low-power applications. There are two major challenges in designing an HTM processor: 1) the massive number of multiplications and divisions used in the algorithm and 2) the large parameter memory storage. We use the Logarithmic Number System (LNS) to simplify the computations, and propose a model compression method that greatly reduces the required storage (a compression ratio of 32 in the experiment). Our design achieves high throughput by maximizing bus utilization. We also propose the Single-Model, Multiple-Image (SMMI) architecture that has high scalability. Using TSMC 40nm technology, our final chip implementation of the HTM processor has an area of 3.63 mm2 and a throughput of 228 objects per second, a 12 times speedup compared with the software implementation.