Converting Interfaces on Application-specific Network-on-chip

Kyuseung Han; Jae-Jin Lee; Woojoo Lee

doi:10.5573/JSTS.2017.17.4.505

주제분류

...

저널정보

대한전자공학회
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 학술저널
Journal of Semiconductor Technology and Science Vol.17 No.4
2017.8 505 - 513 (9page)
DOI : 10.5573/JSTS.2017.17.4.505

저자정보

Kyuseung Han (Electronics and Telecommunications Research Institute)
Jae-Jin Lee (Electronics and Telecommunications Research Institute)
Woojoo Lee (Myongji University)

이용수
내서재: 0

내서재에 추가
되었습니다. 내서재에서
삭제되었습니다.

초록·키워드

오류제보하기

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGAproven full-custom ASNoC.

#Network-on-chip #NoC #application-specific NoC #SoC #processor #computer architecture

참고문헌 (30)

참고문헌 신청

S. Murali et al., “Designing Application-specific Networks on Chips with Floorplan Information,” in Proc. of the Int’l Conf. on Computer-Aided Design, pp. 355?362, 2006. M. Dall’Osso et al., “Xpipes: A latency insensitive parameter- ized network-on-chip architecture for multi-processor SoCs,” in Proc. of the IEEE Int’l Conf. on Computer Design, pp. 45?48, 2012. D. Zhu et al., “TAPP: Temperature-aware pplication mapping for NoC-based many-core processors,” in Proc. of the Int’l Conf.. on Design, Automation & Test in Europe, pp. 1241?1244, 2015. W. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003.

P. P. Pande et al., “Performance evaluation and design trade-offs for network-on-chip interconnect architectures,” IEEE Trans. Comput., vol. 54, pp. 1025?1040, Aug 2005.