Design of High-Speed Comparators for High-Speed Automatic Test Equipment

Byunghun Yoon; Shin-Il Lim

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IEIE Transactions on Smart Processing & Computing 학술저널
IEIE Transactions on Smart Processing & Computing Vol.4 No.4
2015.8 291 - 296 (6page)

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Byunghun Yoon (Seokyeong University)
Shin-Il Lim (Seokyeong University)

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This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with 0.18μm Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is 0.514㎟.

#ATE #High-speed continuous comparator #Hysteresis #Differential difference amplifier