|
[1]
|
R. Yousry, E. Hegazi and H. F. Ragai, “A Third-Order 9-Bit 10-MHz CMOS Modulator with One Active Stage,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 55, No. 9, 2008, pp. 2469-2482.
|
|
[2]
|
C. Sandner, M. Clara, A. Santner, T. Hartig and F. Kuttner, “A 6-Bit 1.2-GS/s Low-Power Flash-ADC in 0.13 μm Digital CMOS,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 7, 2005, pp. 1499-1505.
|
|
[3]
|
P. Nuzzo, P. Van Der Plas, G. De Bernardinis, R. Van Der Perre, L. Gyselinckx and B. Terreni, “A 10.6Mw/ 0.8Pj Power-Scalable 1Gs/S 4B Adc in 0.18/Spl Mu/M Cmos with 5.8Ghz Erbw,” The 43rd ACM/IEEE of the Design Automation Conference, San Francisco, 2006, pp. 873-878.
|
|
[4]
|
K. Uyttenhove and M. S. J. Steyaert, “A 1.8-V 6-Bit 1.3-Ghz Flash Adc in 0.25-ΜM Cmos,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, 2003.
|
|
[5]
|
M. F. Chang, “Semiconductor Technology Considerations in High Speed Data Conversion,” IEEE of Compound Semiconductor Integrated Circuit Symposium, 2004, pp. 31-34.
|
|
[6]
|
G. L. Madhumati, K. Ramakoteswara Rao and M. Madhavilatha, “Comparison of 5-Bit Thermometer-to-Binary Decoders in 1.8 V, 0.18 μm CMOS Technology for Flash ADCs,” 2009 International Conference on Signal Processing Systems, Singapore, 15-17 May 2009, pp. 516-520.
|
|
[7]
|
S. Sheikhaei, S. Mirabbasi and A. Ivanov, “An Encoder for a 5 GS/s 4-Bit Flash ADC in 0.18 μm CMOS,” Canadian Conference of the Electrical and Computer Engineering, May 2005, pp. 698-701.
|
|
[8]
|
T. A. Al Smadi, “Computer Application Using Low Cost Smart Sensor,” International Journal of Computer Aided Engineering and Technology, Vol. 4, No. 6, 2012, pp. 567-579. http://dx.doi.org/10.1504/IJCAET.2012.049572
|
|
[9]
|
Y. Lavania, G. T. Varghese and K. K. Mahapatra, “An Ultra Low Power Encoder for 5 Bit Flash ADC,” International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013, pp. 1-5.
|
|
[10]
|
M. S. Nguyen and J. Kim, “Design and Implementation of Double Base Integer Encoder in the Flash ADC,” The 6th International Conference on Electrical Engineering, Pattaya, 6-9 May 2009, pp. 496-499.
|
|
[11]
|
K. Uyttenhove and M. Steyaert, “Speed-Power-Accuracy Tradeoff in High-Speed CMOS ADCs,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 4, pp. 280-287.
http://dx.doi.org/10.1109/TCSII.2002.801191
|