Impact of Subsurface Damage on SiC Wafer Shape

Kevin Moeggenborg; Ian Manning; Jon Searson; Gil Yong Chung

doi:10.4028/www.scientific.net/MSF.963.530

Paper Titles

Surface Effects of Passivation within Mo/4H-SiC Schottky Diodes through MOS Analysis
p.511

Deep Level Transient Spectroscopy (DLTS) Study of 4H-SiC Schottky Diodes and PiN Diodes
p.516

Chlorine Trifluoride Gas Distributor Design for Single-Crystalline C-Face 4H-Silicon Carbide Wafer Etcher
p.520

High-Efficiency Planarization of SiC Wafers by Water-CARE (Catalyst-Referred Etching) Employing Photoelectrochemical Oxidation
p.525

Impact of Subsurface Damage on SiC Wafer Shape
p.530

Study of 4H-SiC Superjunction Schottky Rectifiers with Implanted P-Pillars
p.539

Surge Current and Avalanche Robustness of Commercial 1200 V SiC Schottky Diodes
p.544

Influence of Trench Design on the Electrical Properties of 650V 4H-SiC JBS Diodes
p.549

The Impact of Non-Ideal Ohmic Contacts on the Performance of High-Voltage SiC MPS Diodes
p.553

HomeMaterials Science ForumMaterials Science Forum Vol. 963Impact of Subsurface Damage on SiC Wafer Shape

Impact of Subsurface Damage on SiC Wafer Shape

Abstract:

The impact of surface stress due to polish and grind processes on wafer bow was studied as a function of abrasive size. Results indicate that sub-surface damage from these processes can introduce significant surface stress. For polishing processes, this stress is proportional to mean abrasive size. The study also investigates stress as a function of depth below the wafer surface and finds that most stress is concentrated near the wafer surface.

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Periodical:

Materials Science Forum (Volume 963)

Pages:

530-533

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.963.530

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Online since:

July 2019

Authors:

Kevin Moeggenborg*, Ian Manning, Jon Searson, Gil Yong Chung

Keywords:

Bow, Grind, Polish, Roughness, SSD, Sub-Surface Damage, Warp

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* - Corresponding Author

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