Direct Observation of Dielectric Breakdown at Step-Bunching on 4H-SiC
p.468
p.468
Evaluation of F-N Tunneling Emission Current in MOS Capacitor Fabricated on Step Bunching
p.472
p.472
Influence of Annealing, Oxidation and Doping on Conduction-Band near Interface Traps in 4H-SiC Characterized by Low Temperature Conductance Measurements
p.476
p.476
Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO2 Interfaces
p.480
p.480
Improving Interface Quality of 4H-SiC MOS Devices with High Temperature Oxidation Process in Mass Produce Furnace
p.484
p.484
Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation
p.488
p.488
Influence of Phosphorous Auto-Doping on the Characteristics of SiO2/SiC Gate Dielectrics
p.492
p.492
Influence of Phosphorus Implantation on Electrical Properties of Al/SiO2/4H-SiC MOS Structure
p.496
p.496
Characteristics of MOS Capacitors with NO and POCl3 Annealed Gate Oxides on (0001), (11-20) and (000-1) 4H-SiC
p.500
p.500
Improving Interface Quality of 4H-SiC MOS Devices with High Temperature Oxidation Process in Mass Produce Furnace
Abstract:
A high-temperature process is used to enhance the COx desorption rate to reduce trap density in SiC/SiO2 interface for SiC MOSFETs. Interface state density as measured by Terman method and C-ψs method for the oxidation processes at a high temperature of 1350°C show significant improvement compared to traditional Si thermal oxidation temperature of 1200°C. The higher oxidation temperature led to a much faster growth rate and some observable hysteresis in the CV curves, which could be due to electron trap and can be resolved by NOx post oxidation anneal (POA).
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Info:
Periodical:
Materials Science Forum (Volumes 821-823)
Pages:
484-487
Citation:
Online since:
June 2015
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