The ASIC Design and Verification Based on Verilog HDL

Yu Ying Yuan; Yong Gang Luo

doi:10.4028/www.scientific.net/AMR.433-440.4578

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 433-440The ASIC Design and Verification Based on Verilog...

The ASIC Design and Verification Based on Verilog HDL

Abstract:

Logic design and verification is the frontend of ASIC (Application Specific Integrated Circuit), and is a very important design part during the design process of ASIC. A Verilog HDL design case－2×2 SDH digital cross-connect matrix is provided to illustrate the entire design process including logic-level description, verification and synthesis based on the frontend tools of Synopsys. After that a gate-level netlist conforming to the design requirements can be obtained.

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Periodical:

Advanced Materials Research (Volumes 433-440)

Pages:

4578-4583

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.433-440.4578

Citation:

Cite this paper

Online since:

January 2012

Authors:

Yu Ying Yuan, Yong Gang Luo

Keywords:

ASIC, HDL, Logic Design, SDXC, Verification

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References

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