Impact of structural parameter scaling on on-state voltage in 1200 V scaled IGBTs

As the worldwide electric power demand is rapidly increasing, developments of high efficiency power electronics are important.^1–4) While many power devices with wide bandgap materials, such as SiC, GaN, and Ga₂O₃, are being developed,^5–9) Si-IGBTs (insulated gate bipolar transistors) are still the main stream power switching devices and are making steady progress by various new technologies.^10–24) The recently proposed three-dimensional scaling concept is one of the effective ways to enhance the Si-IGBT performance.²⁵⁾ In the scaling concept, similarly to the CMOS scaling, all the geometrical dimensions as well as gate voltage are scaled down proportionately while keeping the cell pitch W constant, as shown in Fig. 1.

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In our previous study, we have demonstrated both improved on-stage voltage (V_cesat) and reduced turn-off loss (E_off) in 1200 V-10 A class scaled IGBTs²⁶⁾ designed based on the scaling concept.²⁷⁾ The full size 10A-class IGBT chips had 5 mm² of active emitter area,²⁶⁾ which was large enough to attain 10 A class on-current. However, since the comparisons were made only between non-scaled and scaled IGBTs where multiple structural parameters are changed at the same time, details of the effects of individual scaling parameters remained unclear and the origin of the improved performance should be made clearer. For this purpose, smaller area IGBT test devices (0.144 mm² active emitter area) with a wider variety of combinations of the device parameters were fabricated and their on-state voltage drop (V_cesat) was systematically evaluated.²⁸⁾ This paper describes the work in²⁸⁾ in more detail, and provides additional data on the parameter dependence.

In the scaling concept for Si-IGBTs (Fig. 1), all the geometrical dimensions of the trench region, i.e. mesa width (S), trench depth (D_T), p-base depth (D_P) and gate oxide thickness (t_ox), are scaled down proportionally by a factor of 1/k, while keeping the cell pitch (W) constant, where k is the scaling factor. According to the reduction of the gate oxide thickness, gate voltage is also decreased from 15 to 5 V. The gate voltage reduction will drastically reduce the gate drive power by 1/9, considering that the gate capacitance is kept constant. Although the gate voltage reduction may increase the risk of switching failure, we have already demonstrated 5 V driven turn-off switching without noticeable degradation of the 1200 V 10 A-class IGBTs.²⁶⁾

Figure 2 shows a photograph of the 1200 V IGBT chips fabricated on a 3 inch wafer. In addition to the 10 A-class main chips, test element group (TEG) chips were prepared, each containing 16 smaller area test IGBTs.^29,30) These TEG chip IGBTs consist of 9 pairs of trench gates whose length is 1 mm (active emitter area: 0.144 mm²), with 6 pairs of dummy trench gates on both sides (Fig. 3). The reduce size makes it possible to fabricate a wide variety of IGBTs with different layout design on the same chip. Though a p-float and n-stop pads are provided, which are connected to the p-float and n-base regions (see Fig. 1) at the perimeter of the device, these terminals were not used and kept floated.

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Table I shows the design of experiment (DOE) for this work. "1/3" and "1" in the table indicate whether the parameter is scaled by 1/3 or not. The devices labeled k = 1 and k = 3 are reference non-scaled and fully scaled IGBTs, respectively. Note that while W and S are determined by the layout, D_T, D_P and t_OX are changed by process conditions. A group of parameters related to the MOS gated region D_P, t_ox and V_g are always changed simultaneously. In addition to these structural parameters, p-collector dose was also varied. As a result, 14 types of devices were fabricated in total, as shown in Table I. Figure 4 graphically illustrates the DOE in Table I. The parameter values of designed structure and doping concentration for k = 1 (device A) and k = 3 (device F) are listed in Table II.

Table I.  Structural parameters and sample labels of scaled IGBTs.

		NO scaling (k = 1)	$\mathop{{\rm{Partial}}\,{\rm{scaling}}}\limits_{\longrightarrow}$				Full scaling (k = 3)
Cell pitch, W		1	1	1	1	1	1
Mese width, S		1	1/3	1	1/3	1	1/3
Trench depth, DT		1	1	1	1	1/3	1/3
p-base depth, DP		1	1	1/3	1/3	1/3	1/3
Gate oxide thickness, tox
Gate voltage, Vg
		Sample labels
	×1/2	A−	B−			E−	F−
P-collector dose	×1(typ.)	A	B	C	D	E	F
	×2	A+	B+			E+	F+

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Figure 5 shows simulated carrier distributions for the k = 1 and k = 3 devices for the same p-collector doping of 8.0 × 10¹⁷ cm⁻³ when a collector-emitter current density J_ce of 200 A cm⁻² is flowing. Other parameters of thickness and doping concentration are shown in the figure. It can be seen that, by scaling the device from k = 1 to k = 3, the front side carrier concentration can be selectively increased by the injection enhancement (IE) effect.³¹⁾ On the other hand, the backside carrier concentration, which is primarily determined by the backside device design including the p-collector doping, is not much changed. Therefore, it is expected that the k = 3 device can decrease the V_cesat without degrading turn-off loss, which is closely correlated with the on-state carrier concentration near the back side of the n-base region.

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Figure 6 compares J_ce–V_ce characteristics of main chip IGBT and TEG chip IGBT for both k = 1 and k = 3 devices. The V_cesat in the TEG chips are significantly reduced from the main chips for both k = 1 and k = 3 IGBTs. This can be explained by the fact that the p-float region of the main chips are weakly connected to ground for stable switching operations.²⁶⁾ By connecting the p-floating region to ground, though the switching stability is improved, the IE effect is weakened due to increased hole sinking via the p-float region, and the V_cesat is increased. Since the IE effect is sensitive to the p-float grounding condition, in this work, the p-float terminal was floated for the TEG chip measurements to avoid complication. Figure 7 compares J_ce–V_ce characteristics of the TEG chip IGBTs with the TCAD simulation results corresponding to Fig. 5. The p-float regions are fully floated in both cases. Good agreement was confirmed. The scaling from k = 1 to k = 3 reduced the V_cesat defined at J_ce = 200 A cm⁻² by 0.14 V.

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Measured collector-emitter current versus gate-emitter voltage (I_ce–V_ge) characteristics of the TEG chip devices listed in Table I are shown Fig. 8. The k = 1 group (A⁻, A, A⁺, B⁻, B, B⁺, MOS gated region is not scaled) and the k = 3 (E⁻, E, E⁺, F⁻, F, F⁺, MOS gated region is scaled) group devices (see Table I) respectively show almost identical curves irrespective of mesa width, trench depth, and p-collector dose. Threshold voltages (V_th) of the k = 3 group are adjusted to 1/3 that of the k = 1 group by reducing the gate oxide thickness and controlling the p-base doping concentration. The transconductance for the k = 3 group devices was improved by the gate oxide scaling. Figure 9 shows histograms of V_th for the k = 1 group and k = 3 group IGBTs where V_th is defined at J_ce = 2 A cm⁻². Thanks to the scaled gate oxide thickness, the k = 3 group device exhibit reduced V_th variability.

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It is considered that changing the design parameters will affect IGBT performance in multiple ways as shown in Table III. Mesa width S and trench depth D_T will affect both IE effect and parasitic resistance in opposite ways. Narrower mesa and deeper trench will enhance the IE effect through the increase of hole accumulation, but increase parasitic resistance in the n-mesa region (i.e. between the p-base bottom and the trench bottom). Reduction of p-base depth D_P will reduce the n-channel resistance of trench gate region. Though the cell pitch W will also affect the performance in multiple ways, it was not changed in the scaling. Because the impact of W is less than other parameters, and optimum point of k = 1 and k = 3 is almost same.²⁵⁾ The improved V_cesat by the scaling (Fig. 7) is considered to be caused by the combination of these effects excluding those related to W. The DOE in Table I and Fig. 4 makes it possible to experimentally examine the various effects shown in Table III separately.

Figure 10 shows the impact of mesa width change for both k = 1 (A) and k = 3 (F) IGBTs. One trend of recent IGBT development is narrowing of the mesa width^32–36) for enhancing IE effect. However, Fig. 10 suggests that the performance improvement by further narrowing the mesa in non-scaled IGBT is limited. On the other hand, mesa width dependence of the scaled IGBTs, whose trench depth is shallower and MOS channel is shorter, is larger than that of the non-scaled IGBTs.

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Figure 11 shows the transition from device A (k = 1) to device E through device C. In device C, only MOS gated region (p-base depth and gate oxide thickness) was scaled from device A, whereas mesa width and trench depth are kept the same. In this case, reduction of the MOS channel resistance is considered to be the main contributor to the V_cesat reduction. In device E, trench depth was scaled from device C while keeping the same mesa width. The V_cesat was degraded due to reduced IE effect in this direction. Figure 12 shows the transition from device B to device F (k = 3) through device D. Similarly to Fig. 11, the V_cesat was improved from device B to D. On the other hand, unlike Fig. 11, it can be seen that the increase of the V_cesat from device D to F is almost suppressed. This suggest that reduced IE effect is effectively compensated by the reduction of n-mesa resistance.

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Figure 13 summarizes the V_cesat change from device A (k = 1) to device F (k = 3) through partial scaling (device B– E). Starting from device A, narrowing mesa width (A–B) and shortening the p-base depth (A–C) achieved V_cesat reduction, which were attributed to enhanced IE effect and reduced channel resistance, respectively. Combination of these two can realize further reduction of the V_cesat (A–D). According to the proposed scaling rule, the trench depth should be also scaled down proportionally with the gate oxide thickness, since the gate capacitance has to be kept constant. Though this will suppress IE effect (C–E), this negative impact was compensated by reduced parasitic resistance for the case of D–F. As already pointed out referring to Fig. 10, narrowing the mesa from E–F achieves much larger improvement than A–B. This suggests that the proposed scaling rule that include vertical scaling can enlarge the room for optimization.

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Next, the dependence on back side p-collector dose of J_ce–V_ce curves for both non-scaled and fully scaled IGBTs are shown in Fig. 14. It was found that V_cesat improves with p-collector dose more in k = 3 than k = 1. As is well known, V_cesat can be controlled by simply changing the p-collector dose. However, if the p-collector dose is increased to reduce V_cesat, the on-state carrier concentration in the n-base region, particularly near the back side, is increased, and the switching loss is degraded. Therefore, it is important to achieve low V_cesat, while keeping the back side doping as low as possible. One advantage of scaled IGBTs is the higher on-state carrier concentration near the front side, as was shown in Fig. 5, which is beneficial for lowering V_cesat without increasing the back side doping. In addition to this, Fig. 14 shows that scaled IGBTs will have higher controllability of V_cesat, which will be beneficial for device optimization.

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Measured dependences of V_cesat on P-collector does are summarized in Fig. 15. It can be confirmed that V_cesat of the k = 3 devices show larger sensitivity to not only the mesa width but also p-collector doping. The results suggest again that the proposed scaling can enlarge the possibility of performance improvement than simple mesa width scaling.

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Structural parameter dependence of 1200 V IGBT J_ce–V_ce characteristics was systematically studied in order to explore the possibility of further performance improvement by the parameter scaling. Measurements without complication by p-float grounding were achieved using small scale IGBT test devices. It was confirmed that both MOS channel resistance reduction and increased IE effect are responsible for the improved V_cesat of the scaled devices. It was also found that the scaled devices show larger dependence of V_cesat on p-collector dose and mesa width. This suggests that IGBT scaling will be effective for enlarging the design space to achieve better performance.

The authors would like to thank K. Sato of Mitsubishi Electric Corp., Dr. T. Matsudai of Toshiba Electronic Devices & Storage Corp., Dr. M. Tsukuda of Green Electronics Research Institute, and Prof. W. Saito of Kyushu University for fruitful discussions. This work is based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO).