A High-Efficiency Isolated LCLC Multi-Resonant Three-Port Bidirectional DC-DC Converter

Abstract

In this paper, an isolated multi-resonant three-port bidirectional direct current-direct current (DC-DC) converter is proposed, which is composed of three full bridges, two inductor-capacitor-inductor-capacitor (LCLC) multi-resonant tanks and a three-winding transformer. The phase shift control method is employed to manage the power transmission among three ports. Relying on the appropriate parameter selection, both of the fundamental and the third order power can be delivered through the multi-element LCLC resonant tanks, and consequently, it contributes to restrained circulating energy and the desirable promoted efficiency. Besides, by adjusting the driving frequency under different load conditions, zero-voltage-switching (ZVS) characteristics of all the switches of three ports are guaranteed. Therefore, lower switching loss and higher efficiency are achieved in full load range. In order to verify the feasibility of the proposed topology, a 1.5 kW prototype is established, of which the maximum efficiencies under forward and reverse operating conditions are 96.7% and 96.9% respectively. In addition, both of the bidirectional efficiencies maintain higher than 95.5% when the power level is above 0.5 kW.

1. Introduction

Nowadays, facing the increasingly severe energy crisis and pollution issues, considerable attention is being focused on renewable power sources to figure out promising solutions [1,2,3]. However, owing to the time-varying and intermittent output features of some renewable sources, energy storage plays an indispensable role to improve the stability and energy utilization rate of the distributed energy generation system (DEGS) [4,5,6]. In existing DEGS, the renewable energy sources, storage units and loads are connected together by their independent converters. Therefore, the large number of converters leads to complexity in the DEGS architecture. This issue is addressed by adopting three-port converters, where the efficiency, the cost and the power density are optimized. As a consequence, three-port bidirectional DC-DC converters (TP-BDCs) have become a competitive alternative in recent years.

Based on the connections, the TP-BDCs are simply categorized into three types, namely the non-isolated, the partly-isolated and the isolated converters [7]. For the non-isolated topology, although the direct connection is beneficial for its reduced number of components and compact architecture, this kind of TP-BDC suffers from limited voltage gain, since the voltage conversion ratio can only be adjusted by controlling the duty-ratio of switches [8,9,10]. In the partly-isolated structures, a transformer is used to isolate one port from the other two ports. Owing to the added transformer, is easier to obtain higher voltage gain with the partly-isolated TP-BDC [11,12,13,14]. However, neither non-isolated or partly-isolated TP-BDCs are suitable for applications where the three ports must be completely isolated. Therefore, it is necessary to consider the isolated-type TP-BDC [15,16].

The isolated TP-BDC exhibits pronounced advantages over its two counterparts, since the three-port power exchanges are realized through a three-winding high-frequency transformer, and the completely galvanic isolation is also ensured. Furtherly, among the numerous previously published references [17,18,19,20,21,22,23,24] about isolated TP-BDCs, two more detailed main sub-classifications are used: the triple-active-bridge (TAB) converter shown in Figure 1a and the series-resonant TP-BDC (SR-TP-BDC) in Figure 1b.

The TAB converter, a research hotspot, is composed of three active bridges, three inductors and a three-winding transformer [17,18,19,20,21]. It possesses advantages such as galvanic isolation, bidirectional power flow, ZVS operation and phase shift control with fixed switching frequency, while the power coupling among the three ports makes the decoupling matrix essential in its control loop, which is sophisticated and can be detrimental to the reliability of TAB. Moreover, the power transmission in TAB topology is in inverse proportion of the impedance of L₁–L₃, and L₁–L₃ are inherent greater than the leakage inductors of transformer. Consequently, the switching frequency has to be reduced in case of high power levels. In [19,20,21] the driving frequencies are all 20 kHz, and this will be detrimental for the desired high power density.

The other sub-classification is the series-resonant TP-BDC (SR-TP-BDC) as Figure 1b shows. Compared to TAB, the SR-TP-BDC introduces two additional series-resonant tanks into the primary sides. For one thing, it maintains the main advantages of TAB such as galvanic isolation, bidirectional operation, ZVS features and constant switching frequency [22,23,24]. For another, the decoupling of the power transmissions successfully relieves the difficulty of control issue. Additionally, another benefit of SR-TP-BDC is that the impedance of SR tanks can be regulated by C_r1, L_r1, C_r2, L_r2 and the driving frequency together, thus, it can operate with a higher switching frequency with realizable component values under high power level. In [23,24], renewable source, battery and load are integrated to a three-port SR BDC. The driving frequency rises to 100 kHz, which is apparently higher than 20 kHz of TAB [19,20,21].

In spite of the benefits discussed above, the SR-TP-BDC still needs to be modified due to the loss of ZVS at light load. Since the phase shift angle is small under light load conditions, the energy stored in the series-resonant tanks is unable to fully discharge the switches’ output capacitors. In order to improve the operating characteristics of series resonant converter under light load conditions, many studies have been conducted [25,26,27,28,29,30]. In [29], an additional capacitor is added to the resonant storage to solve the regulation problem in which the output voltage increases as the load current decreases. Moreover, all the advantages of typical inductor-inductor-capacitor (LLC) series-resonant converter (SRC) are maintained in this article. In [30], additional unidirectional switch and pulse width modulation (PWM) are introduced to the traditional half-bridge SRC to limit the operating frequency under light load. Then the light-load efficiency is elevated as the following result. Nevertheless, both these methods mentioned above are based on the single input and single output converter with frequency modulation method (PFM), and cannot extend to the application of TP-BDCs with the phase shift control method. Another serious drawback of SR-TP-BDC is that the series-resonant storage can only transfer the fundamental power, while the higher order harmonic power, inducing the reactive power, will bring in circulating power and hence sacrifices the nominal efficiency.

To alleviate the aforementioned drawbacks, a novel isolated multi-resonant TP-BDC (MR-TP-BDC) is developed in this article. The LCLC resonant storage exploited in this article has three resonant frequencies, namely a 2nd harmonic parallel resonant frequency and two series resonant frequencies. These two series resonant points, arranged 1st and 3rd, respectively, guarantee the active power deliveries for the fundamental and the third order, by which the circulating energy is constrained. Besides, through properly adjusting the operating frequency for diverse load states, the proposed MR-TP-BDC obtains the fruitful ZVS traits for all the switches of the three ports among whole load range. Finally, a prototype platform is fabricated to verify the theoretical analyses. The article is organized as followings: the operating principles of the proposed converter is given in Section 2. The steady-state analysis is introduced in Section 3. Parameters optimization design is presented in Section 4. Finally, the experimental results are presented in Section 5, and the conclusion is drawn in Section 6. The features of the proposed isolated MR-TP-BDC are:

(1)

The three-port power exchanges are multi-directional, and the centralized phase shift control method is utilized to manage the power flows.

(2)

The transportation of the extra 3rd power contributes to the reduced circulating power.

(3)

ZVS characteristics of all switches in the three ports are guaranteed within the whole load range.

(4)

The proposed converter is proved to have high efficiency among entire load range. High efficiencies of over 95.5% is acquired for bidirectional operation on the condition that the power level is above 0.5 kW. Meanwhile, the highest efficiencies of the forward and reverse modes are 96.7% and 96.9% respectively.

2. Operating Principle of the Proposed Converter

The proposed MR-TP-BDC is presented in Figure 2, and it is made up of four main parts including a three-winding transformer, three full bridges, two MR tanks and three filter capacitors C_F1–C_F3. Phase shift control method is implemented, the amount and direction of transmitted power is controlled by the phase shift angles. Two switches of the same bridge leg conduct complementarily with fixed duty ratio of 50%. The operating frequency f_s is above the resonant frequency of MR tanks to ensure the converter works only in continuous current mode.

To simplify the analysis, we assume the voltages of three ports to be constant dc. Therefore, v_T1, v_T2 and v_T3 are square-waves with amplitudes of ±V₁, ±V₂ and ±V₃, respectively. The phase shift angles of port 1 and 2 are defined as ϕ₁₃ and ϕ₂₃, and they control the phase shifts among the square wave outputs of the three active bridges. ϕ₁₃ and ϕ₂₃ are defined as positive if v_T1 and v_T2 lead v_T3, and conversely, ϕ₁₃ and ϕ₂₃ are considered negative.

The MR tanks are made up of C_R, L_R, C_P and L_P, and in order to simplify the parameter design, resonant parameters of port 1 and 2 are set identical. The MR tanks have two series resonant frequencies (SRFs), which are defined as f_r and f_r3 respectively, and a notch resonant frequency (NRF) f_r2. The first SRF f_r helps to deliver the fundamental component energy. To avoid additional power circulation, NRF should de designed at even times of the nominal resonant frequency f_r, and 2f_r is selected. The second SRF, placed at 3f_r, ensures the transfer of the 3rd harmonic power and thus shows significance on circulating energy reduction and efficiency saving.

The parameters are defined as follows: V₁-V₃ are the voltages of three ports, v_T1–v_T3 are the voltages of the square wave outputs of three active bridges, i₁–i₃ are the currents of three ports, i_T1–i_T3 are the resonant currents of three ports, i_P1–i_P3 are the currents of three full bridges; v_CR1–v_CR2 are the voltages of C_R1 and C_R2; v_CP1–v_CP2 are the voltages C_P1 and C_P2; i_LP1–i_LP2 are the currents of L_P1 and L_P2 and P₁–P₃ are the power of three ports. The positive direction of each value is shown in Figure 2.

Limited by the length of the article, only the operating principle for a certain case is presented, for instance, where the power flows from port 1 and 2 to port 3. In this condition, ϕ₁₃ > ϕ₂₃ > 0, and the theoretical waveforms are as shown in Figure 3.

The dead time is taken into consideration, while the short intervals of the charging and discharging of switches’ parasitic output capacitors are neglected. Totally, there are 12 different intervals existing in one switching cycle, and the equivalent circuits of each stage are shown in Figure 4:

Stage 1 (t₀–t₁): This interval begins at the t₀ when S₂ and S₃ are turned off, and it is dead time of port 1. During this interval, S₆ and S₇, S₁₀ and S₁₁ are on. Since i_T1 is negative, it flows through D_s1 and D_s4, the anti-parallel diodes of S₁ and S₄. i_T2 flows through S₆ and S₇, i_T3 flows through S₁₀ and S₁₁. The current flow paths and directions of three ports are shown in Figure 4a. This stage ends at t₁, when S₁ and S₄ are turned on.

Stage 2 (t₁–t₂): During this stage, S₁ and S₄, S₆ and S₇, S₁₀ and S₁₁ are on. i_T1, i_T2 and i_T3 flow through S₁ and S₄, S₆ and S₇, S₁₀ and S₁₁ respectively, as shown in Figure 4b. D_s1 and D_s4 conduct prior to the main switches of S₁ and S₄, thus, S₁ and S₄ are turned on with ZVS. This stage ends at t₂, when S₆ and S₇ are turned off.

Stage 3 (t₂–t₃): This stage is dead time of port 2, S₁ and S₄, S₁₀ and S₁₁ are on. i_T1 and i_T3 flow through S₁ and S₄, S₁₀ and S₁₁ respectively. i_T2 is negative, so i_T2 flows through the anti-parallel diodes of S₅ and S₈. The current flow paths and directions of three ports are shown in Figure 4c, while the current directions of port 1 and 3 change in this interval, so only the current paths of i_T1 and i_T3 are given. This interval ends at t₃, when S₅ and S₈ are turned on.

Stage 4 (t₃–t₄): During this stage, S₁ and S₄, S₅ and S₈, S₁₀ and S₁₁ are on. i_T1, i_T2 and i_T3 flow through S₁ and S₄, S₅ and S₈, S₁₀ and S₁₁ respectively. D_s5 and D_s8 conduct prior to the main switches of S₅ and S₈, thus, S₅ and S₈ are turned on with ZVS. The operating states of three ports are shown in Figure 4d. In this stage the direction of i_T2 changes, so only the current path of port 2 are given. This stage ends at t₄, when S₁₀ and S₁₁ are turned off.

Stage 5 (t₄–t₅): During this stage, S₁ and S₄, S₅ and S₈ are on, and this interval is dead time of port 3. i_T1 and i_T2 flow through S₁ and S₄, S₅ and S₈ respectively. i_T3 is positive, so it flows through the anti-parallel diodes of S₉ and S₁₂. The operating states of three ports are shown in Figure 4e. This interval ends at t₅, when S₉ and S₁₂ are turned on.

Stage 6 (t₅–t₆): During this stage, S₁ and S₄, S₅ and S₈, S₉ and S₁₂ are on. As shown in Figure 4f, i_T1, i_T2 and i_T3 flow through S₁ and S₄, S₅ and S₈, S₉ and S₁₂ respectively. D_s9 and D_s12 conduct prior to the main switches of S₉ and S₁₂, thus, S₉ and S₁₂ are turned on with ZVS. This stage ends at t₆, when S₁ and S₄ are turned off.

Stage 7 (t₆–t₇): This stage is dead time of port 1. During this interval, S₅ and S₈, S₉ and S₁₂ are on. Since i_T1 is positive, it flows through D_s2 and D_s3, the anti-parallel diodes of S₂ and S₃. i_T2 flows through S₅ and S₈, i_T3 flows through S₉ and S₁₂. The current flow paths and directions of three ports are shown in Figure 4g. This stage ends at t₇, when S₂ and S₃ are turned on.

Stage 8 (t₇–t₈): During this stage, S₂ and S₃, S₅ and S₈, S₉ and S₁₂ are on. As shown in Figure 4h, i_T1, i_T2 and i_T3 flow through S₂ and S₃, S₅ and S₈, S₉ and S₁₂ respectively. D_s2 and D_s3 conduct prior to the main switches of S₂ and S₃, thus, S₂ and S₃ are turned on with ZVS. This stage ends at t₈, when S₅ and S₈ are turned off.

Stage 9 (t₈–t₉): This stage is dead time of port 2. During this interval, S₂ and S₃, S₉ and S₁₂ are on. Since i_T2 is positive, it flows through D_s6 and D_s7, the anti-parallel diodes of S₆ and S₇. i_T1 flows through S₂ and S₃, i_T3 flows through S₉ and S₁₂. The operating states of three ports are shown in Figure 4i, while the current directions of port 1 and 3 change in this interval, so only the current paths of i_T1 and i_T3 are given. This interval ends at t₉, when S₆ and S₇ are turned on.

Stage 10 (t₉–t₁₀): During this stage, S₂ and S₃, S₆ and S₇, S₉ and S₁₂ are on. As shown in Figure 4j, i_T1, i_T2 and i_T3 flow through S₂ and S₃, S₆ and S₇, S₉ and S₁₂ respectively. In this stage the direction of i_T2 changes, so only the current path of port 2 is given. D_s6 and D_s7 conduct prior to the main switches of S₆ and S₇, thus, S₆ and S₇ are turned on with ZVS. This stage ends at t₁₀, when S₉ and S₁₂ are turned off.

Stage 11 (t₁₀–t₁₁): This stage is dead time of port 3. During this interval, S₂ and S₃, S₆ and S₇ are on. Since i_T3 is negative, it flows through D_s10 and D_s11, the anti-parallel diodes of S₁₀ and S₁₁. i_T1 flows through S₂ and S₃, i_T2 flows through S₆ and S₇. The operating states of three ports are shown in Figure 4k. This interval ends at t₁₁, when S₁₀ and S₁₁ are turned on.

Stage 12 (t₁₁–t₁₂): During this stage, S₂ and S₃, S₆ and S₇, S₁₀ and S₁₁ are on. As shown in Figure 4l, i_T1, i_T2 and i_T3 flow through S₂ and S₃, S₆ and S₇, S₁₀ and S₁₁ respectively. D_s10 and D_s11 conduct prior to the main switches of S₁₀ and S₁₁, thus, S₁₀ and S₁₁ are turned on with ZVS. This stage ends at t₁₂, when S₂ and S₃ are turned off.

3. Steady-State Analysis

In this section, the steady-state analysis is conducted for the proposed isolated MR-TP-BDC, including expressions of resonant currents, voltages of resonant capacitors, power transmission among three ports and voltage gains under resistive loads.

3.1. Normalization and Definitions

To simplify the circuit analysis and parameter design, the resonant parameters of port 1 and 2 are assumed to be identical, that is C_R1 = C_R2 = C_R, L_R1 = L_R2 = L_R, C_P1 = C_P2 = C_P and L_P1 = L_P2 = L_P. Besides, to facilitate the explanation of the parameter design, all the equations presented are normalized on the basis of Equation (1):

$$V_{\mathrm{B}}=V_3{P}_{\mathrm{B}}=P_3{Z}_{\mathrm{B}}=V_3^2/P_{\mathrm{B}}{I}_{\mathrm{B}}=V_{\mathrm{B}}/Z_{\mathrm{B}}$$

(1)

The normalized driving frequency is shown as Equation (2), where ω_s and ω_r are the corresponding angular velocities of f_s and f_r, respectively:

$$F=\frac{{\omega }_{\mathrm{s}}}{{\omega }_r}=\frac{f_{\mathrm{s}}}{f_{\mathrm{r}}}$$

(2)

The impedance of MR storage under two SRFs (f_r and f_r3) are 0, and impedance under NRF (f_r2) is infinite. Moreover, the relationships of the three resonant frequencies are: f_r2 = 2f_r, f_r3 = 3f_r. Thus, the impedance of MR storage under f_r, f_r2 and f_r3 are defined as X_r1, X_r2 and X_r3, and are deduced in Equation (3):

$$\{\begin{array}{l}{X}_{r1}={\omega }_r{L}_R-\frac{1}{{\omega }_r{C}_R}+\frac{{\omega }_r{L}_P}{1-{{\omega }_r}^2{L}_P{C}_P}=0\\ X_{r2}=2{\omega }_r{L}_R-\frac{1}{2{\omega }_r{C}_R}+\frac{2{\omega }_r{L}_P}{1-4{{\omega }_r}^2{L}_P{C}_P}=\infty \\ X_{r3}=3{\omega }_r{L}_R-\frac{1}{3{\omega }_r{C}_R}+\frac{3{\omega }_r{L}_P}{1-9{{\omega }_r}^2{L}_P{C}_P}=0\end{array}$$

(3)

From (3), the relationship between four resonant parameters are deduced as:

$$C_R=\frac{5}{3}{C}_P,L_R=\frac{16}{15}{L}_P,4{\omega }_r^2=C_P{L}_P$$

(4)

The impedance of MR storage under angular velocity ω is:

$$X=\frac{16}{15}\omega L_P-\frac{12{\omega }_r^2{L}_P}{5\omega }+\frac{4{\omega }_r^2\omega L_P}{4{\omega }_r^2-{\omega }^2}$$

(5)

Combining Equations (4) and (5), the impedance of MR storage under f_s and 3f_s can be expressed as Equation (6).

$$\{\begin{array}{l}{X}_{\mathrm{s}1,\mathrm{pu}}=Q(\frac{16}{15}F-\frac{12}{5F}+\frac{4F}{4-F^2})\\ X_{\mathrm{s}3,\mathrm{pu}}=Q(\frac{16}{5}F-\frac{4}{5F}+\frac{12F}{4-9F^2})\end{array}$$

(6)

where Q is defined as:

$$Q=\frac{{\omega }_r{L}_P}{Z_B}$$

(7)

3.2. Operating Characteristics with Voltage Source Load

The equivalent circuit of the proposed MR-TP-BDC is presented in Figure 5a, where the three square-wave v_T1, v_T2 and v_T3 represent the outputs of the active bridges. By transferring all parameters of port 1 and port 2 to port 3, the equivalent circuit can be further simplified as Figure 5b shows. The superscript “′” indicates the transferred parameters. On account of the complexity of MR tank, the proposed MR-TP-BDC has a plurality of resonant components and operating modes. It will be difficult to analyze the circuit with traditional time-domain analysis method. Therefore, Fourier equivalent method is adopted in the following analysis procedure. The accuracy of the calculation is verified by the experimental results.

In the proposed MR-TP-BDC, all harmonics except the fundamental and third order components of all voltages and currents are neglected. After Fourier decomposition, v′_T1, v′_T2 and v_T3 are shown as:

$$\{\begin{array}{l}{v}_{T1,pu}^{\text{'}}(t)=\frac{4M_1}{\pi }\left[\sin (w_{s}t+{\phi }_{13})+\frac{1}{3}\sin (3w_{s}t+3{\phi }_{13})\right]\\ v_{T2,pu}^{\text{'}}(t)=\frac{4M_2}{\pi }\left[\sin (w_{s}t+{\phi }_{23})+\frac{1}{3}\sin (3w_{s}t+3{\phi }_{23})\right]\\ v_{T3,pu}(t)=\frac{4}{\pi }\left[\sin w_{s}t+\frac{1}{3}\sin (3w_{s}t)\right]\end{array}$$

(8)

M₁ and M₂ are the voltage gains between port1 and port 3, port 2 and port 3 respectively, and are given by Equation (9):

$$\{\begin{array}{l}{M}_1=\frac{V_1}{n_{13}{V}_B}\\ M_2=\frac{V_2}{n_{23}{V}_B}\end{array}$$

(9)

Assume the transformer to be ideal, and the transformer voltage is clamped by the voltage of port 3. The currents of port 1 and 2 are decided by their voltage and phase shift angles respectively. The resonance currents shown in Figure 5b are derived as:

$$\{\begin{array}{l}{i}_{T1,pu}^{\text{'}}(t)=\frac{4n_{13}^2}{\pi }\left[\frac{\cos ({\omega }_{s}t)-M_1\cos ({\omega }_{s}t+{\phi }_{13})}{X_{s1,pu}}+\frac{\cos (3{\omega }_{s}t)-M_1\cos (3{\omega }_{s}t+3{\phi }_{13})}{3X_{s3,pu}}\right]\\ i_{T2,pu}^{\text{'}}(t)=\frac{4n_{23}^2}{\pi }\left[\frac{\cos ({\omega }_{s}t)-M_2\cos ({\omega }_{s}t+{\phi }_{23})}{X_{s1,pu}}+\frac{\cos (3{\omega }_{s}t)-M_2\cos (3{\omega }_{s}t+3{\phi }_{23})}{3X_{s3,pu}}\right]\\ i_{T3,pu}(t)=i_{T1,pu}^{\text{'}}(t)+i_{T2,pu}^{\text{'}}(t)\end{array}$$

(10)

The normalized impedance of C_R under f_s and 3f_s are expressed as Equation (11):

$$\{\begin{array}{l}{X}_{\mathrm{CR}1,\mathrm{pu}}=\frac{1}{{\omega }_s{C}_R{Z}_B}\\ X_{\mathrm{CR}3,\mathrm{pu}}=\frac{1}{3{\omega }_s{C}_R{Z}_B}\end{array}$$

(11)

By combining Equations (10) and (11), the voltages of series resonant capacitors are deduced as:

$$\{\begin{array}{l}{v}_{CR1,pu}(t)=\frac{4n_{13}}{\pi }\left[\frac{M_1\sin ({\omega }_{s}t+{\phi }_{13})-\sin ({\omega }_{s}t)}{X_{s1,pu}}{X}_{CR1,pu}+\frac{M_1\mathrm{sins}(3{\omega }_{s}t+3{\phi }_{13})-\sin (3{\omega }_{s}t)}{3X_{s3,pu}}{X}_{CR3,pu}\right]\\ v_{CR2,pu}(t)=\frac{4n_{23}}{\pi }\left[\frac{M_2\sin ({\omega }_{s}t+{\phi }_{23})-\sin ({\omega }_{s}t)}{X_{s1,pu}}{X}_{CR1,pu}+\frac{M_2\mathrm{sins}(3{\omega }_{s}t+3{\phi }_{23})-\sin (3{\omega }_{s}t)}{3X_{s3,pu}}{X}_{CR3,pu}\right]\end{array}$$

(12)

For switches in port 1, the ZVS realizing condition is that the resonant storage current lags its applied square wave voltage. For S₁ and S₄, ZVS will be achieved only on the condition that their currents at the conduction time are negative, while for S₂ and S₃, resonant current at the conduction time should be positive to guarantee ZVS operating. The ZVS constraint conditions of port 1 are expressed as Equation (13):

$$\{\begin{array}{l}{i}_{T1,pu}^{\text{'}}(\frac{-{\phi }_{13}}{{\omega }_S})<0{\mathrm{S}}_1/{\mathrm{S}}_4\\ i_{T1,pu}^{\text{'}}(\frac{-{\phi }_{13}+\pi }{{\omega }_S})>0{\mathrm{S}}_2/{\mathrm{S}}_3\end{array}$$

(13)

According to the properties of the cosine function, the ZVS constraint formulas of the four switches in port 1 are completely equivalent. As a consequence, simple analysis on the ZVS condition for S₁ is enough for port 1. Similarly, ZVS conditions of S₅ and S₉ indicate the ZVS conditions of port 2 and 3. To sum up, the ZVS constraint expressions of three ports are shown in Equation (14):

$$\{\begin{array}{l}{i}_{T1,pu}^{\text{'}}(\frac{-{\phi }_{13}}{{\omega }_S})=\frac{4n_{13}^2}{\pi }[\frac{\cos ({\phi }_{13})-M_1}{X_{s1,pu}}+\frac{\cos (3{\phi }_{13})-M_1}{3X_{s3,pu}}]<0\\ i_{T2,pu}^{\text{'}}(\frac{-{\phi }_{23}}{{\omega }_S})=\frac{4n_{23}^2}{\pi }[\frac{\cos ({\phi }_{23})-M_2}{X_{s1,pu}}+\frac{\cos (3{\phi }_{23})-M_2}{3X_{s3,pu}}]<0\\ i_{T3,pu}(0)=\frac{4n_{13}^2}{\pi }[\frac{1-M_1\cos ({\phi }_{13})}{X_{s1,pu}}+\frac{1-M_1\cos (3{\phi }_{13})}{3X_{s3,pu}}]+\frac{4n_{23}^2}{\pi }[\frac{1-M_2\cos ({\phi }_{23})}{X_{s1,pu}}+\frac{1-M_2\cos (3{\phi }_{23})}{3X_{s3,pu}}]>0\end{array}$$

(14)

Since the instantaneous output voltages and currents of three active bridges are shown in equations (8) and (10), respectively, the output active power of three ports are shown in Equation (15).

$$\{\begin{array}{l}{P}_{1,pu}=\frac{1}{2\pi }{\displaystyle {\int }_0^{2\pi }{v}_{T1,pu}^{\text{'}}(t)i_{T1,pu}^{\text{'}}(t)}d({\omega }_{s}t)\\ P_{2,pu}=\frac{1}{2\pi }{\displaystyle {\int }_0^{2\pi }{v}_{T2,pu}^{\text{'}}(t)i_{T2,pu}^{\text{'}}(t)}d({\omega }_{s}t)\\ P_{3,pu}=P_{1,pu}+P_{2,pu}\end{array}$$

(15)

By substituting Equations (8) and (10) into (15), the output power of three ports are shown in Equation (16):

$$\{\begin{array}{l}{P}_{1,pu}=\frac{8M_1{n}_{13}^2}{{\pi }^2}\left[\frac{\sin {\phi }_{13}}{X_{s1,pu}}+\frac{\sin (3{\phi }_{13})}{9X_{s3,pu}}\right]\\ P_{2,pu}=\frac{8M_2{n}_{23}^2}{{\pi }^2}\left[\frac{\sin {\phi }_{23}}{X_{s1,pu}}+\frac{\sin (3{\phi }_{23})}{9X_{s3,pu}}\right]\\ P_{3,pu}=\frac{8M_1{n}_{13}^2}{{\pi }^2}\left[\frac{\sin {\phi }_{13}}{X_{s1,pu}}+\frac{\sin (3{\phi }_{13})}{9X_{s3,pu}}\right]+\frac{8M_2{n}_{23}^2}{{\pi }^2}\left[\frac{\sin {\phi }_{23}}{X_{s1,pu}}+\frac{\sin (3{\phi }_{23})}{9X_{s3,pu}}\right]\end{array}$$

(16)

Equation (16) indicates that the powers of port 1 and port 2 are only relative to ϕ₁₃ and ϕ₂₃, while P_3,pu are effected by both ϕ₁₃ and ϕ₂₃. Figure 6a shows the relationship between P_1,pu and ϕ₁₃, Figure 6b shows the relationship between P_2,pu and ϕ₂₃, while Figure 6c shows P_3,pu with varying ϕ₁₃ and ϕ₂₃.

Equation (16) and Figure 6 indicate that when ϕ₁₃ and ϕ₂₃ are positive, power is transferred from port 1 and port 2 to port 3, while at the converse situation, the power flow is negative. Furthermore, the values of transferred power increases with the increment of phase shift angles.

3.3. Voltage Gain with Resistive Load

In the analysis above, the operating characteristics of the proposed converter under given port voltages are deduced. This section explains the relationship of voltage gain, power transmission and phase shift angles with a resistive load. The voltage gain analyses are divided into two cases.

In the first case, port 1 and 2 are connected to voltage sources of V₁ and V₂, port 3 is connected to resistive load, and the resistive value is defined as R₃. At this time, the power is transferred from port 1 and port 2 to port 3, and both ϕ₁₃ and ϕ₂₃ are positive. The power of port 3 is P₃ = V₃²/R₃. Combing Equation (16), the power of port 3 will be derived as:

$$P_3=(P_{1,pu}+P_{2,pu})\frac{V_B^2}{Z_B}=\frac{V_3^2}{R_3}$$

(17)

Since the base values for normalization in Equation (1) are the operating parameters of port 3, Equation (17) uses the actual electric values rather than the normalized ones. Combining (16) and (17), the output power in this condition can be expressed as Equation (18):

$$V_3=\frac{8n_{13}{V}_1{R}_3}{{\pi }^2}\left[\frac{\sin {\phi }_{13}}{X_{s1}}+\frac{\sin (3{\phi }_{13})}{9X_{s3}}\right]+\frac{8n_{23}{V}_2{R}_3}{{\pi }^2}\left[\frac{\sin {\phi }_{23}}{X_{s1}}+\frac{\sin (3{\phi }_{23})}{9X_{s3}}\right]$$

(18)

where X_s1 and X_s3 are the impedance values of MR tanks under fundamental frequency and third order frequency, respectively, and X_s1 = X_s1,pu × Z_B, X_s3 = X_s3,pu × Z_B.

In another case, port 3 is connected to a voltage source, and resistive loads R₁ and R₂ are connected to port 1 and 2, respectively. In this condition, power is transferred from port 3 to port 1 and 2, and both ϕ₁₃ and ϕ₂₃ are negative. The power of port 1 and 2 are expressed as: P₁ = V₁²/R₁ and P₂ = V₂²/R₂. By combing Equation (16), P₁ and P₂ are derived as:

$$\{\begin{array}{l}{P}_1=P_{1,pu}\times \frac{V_B^2}{Z_B}=\frac{V_1^2}{R_1}\\ P_2=P_{2,pu}\times \frac{V_B^2}{Z_B}=\frac{V_2^2}{R_2}\end{array}$$

(19)

where V₁ = n₁₃M₁V_B, V₂ = n₂₃M₁₂V_B. Then the voltage gains of port 1 and 2 in this condition are deduced as:

$$\{\begin{array}{l}{M}_1=\frac{8R_{1,pu}}{{\pi }^2}\left[\frac{\sin \left|{\phi }_{13}\right|}{X_{s1,pu}}+\frac{\sin \left|3{\phi }_{13}\right|}{9X_{s3,pu}}\right]\\ M_2=\frac{8R_{2,pu}}{{\pi }^2}\left[\frac{\sin \left|{\phi }_{23}\right|}{X_{s1,pu}}+\frac{\sin \left|3{\phi }_{23}\right|}{9X_{s3,pu}}\right]\end{array}$$

(20)

and R_1,pu = R₁/Z_B, R_2,pu = R₂/Z_B.

4. Design Parameter Optimization

Same as the other resonant converters, the optimization for the resonant parameters is of great importance, since the operating characteristics of the proposed converter are mainly affected by these parameters. The design requirements of the proposed converter are shown as follows:

• Port 1: V₁ = 200 V, P₁ = 1000 W;
• Port 2: V₂ = 160 V, P₂ = 500 W;
• Port 3: V₃ = 400 V, P₃ = 1500 W.

The parameters which need to be optimized include the transformer ratio, values of resonant components and driving frequency. The optimization objectives are ZVS range, peak value of resonant currents, voltage stress of resonant capacitors and cutoff current of switches. And the parameters are optimized in detail in the following.

Since the voltage of transformer is clamped by the voltage of port 3, there is no direct power interaction between port 1 and port 2. It is feasible to decompose the proposed MR-TP-BDC into two single input MR-BDCs, and the design principles of port 1 and port 2 are identical. To simplify the analysis, the operating characteristics of single input MR-BDC are analyzed in this section.

4.1. Transformer Ratio Optimization

The transformer turn ratio affects voltage gain M₁ and M₂ as shown in Equations (8) and (9). Furthermore, Equation (14) indicates the voltage gains directly influence the ZVS realization ranges of three ports. Since there is no direct power interaction between port 1 and port 2, the ZVS realization ranges of port 1 and 3 under single input condition are efficient to analyze the relationship between voltage gain and ZVS region.

The ZVS constraint conditions of three ports are given in (14). In the condition of single input, the ZVS realization conditions of port 1 and 3 are i′_T1,pu(−ϕ₁₃/ω_s) < 0 and i′_T1,pu(0) > 0 respectively. The ZVS regions of port 1 and port 3 under varying M₁ are shown in Figure 7a,b.

Figure 7a indicates that when M₁ is less than or equal to 1, all the switches in port 1 can realize ZVS. When M₁ is greater than 1, switches in port 1 cannot realize ZVS unless ϕ₁₃ (output power) is greater than a certain value. While for port 3 shown in Figure 7b, conditions are exactly contrary to port 1. When M₁ is less than 1, switches in port 3 can only realize ZVS only when the phase shift angel is greater than a certain value. It can be obtained that, the ZVS realization regions of port 1 and port 3 change reversely under varying M₁, so during the design process, M₁ should be as close to 1 as possible, and M₁ = 1 is the best choice to achieve ZVS for all the switches of port 1 and 3.

Conditions of port 2 are exactly the same with port 1, and M₁ = M₂ = 1 are the optimal voltage gains to guarantee ZVS operation of all switches of proposed isolated MR-TP-BDC. According to the given voltages of three ports and voltage gains, turn ratios of transformer are defined as: n₁₃:n₂₃:1 = 0.5:0.4:1.

4.2. Resonant Components Optimization

The MR storage in the proposed converter consists of four resonant elements: resonant capacitors C_R and C_P, resonant inductors L_R and L_P. While there are constraint relations between the four resonant elements as shown in Equation (4). This will greatly reduce the difficulty of parameters design. In the following parameters design process, L_P is selected as the optimization variable. In the considered single-input converter, P_1,pu = P_3,pu, i_T1,pu(t) = i′_T1,pu(t)/n₁₃, i′_T1,pu(−ϕ₁₃/ω_s) = −i_T3,pu(0).

With given voltage gains, resonant parameters and driving frequency, the phase shift angle ϕ₁₃, which can provide certain P_1,pu, will be derived by solving Equation (16). Then substitute ϕ₁₃ into (10), the corresponding cutoff current is expressed as i_T1,pu(-ϕ₁₃/ω_s) = i′_T1,pu(-ϕ₁₃/ω_s)/n₁₃. Through using the function of seeking maximum value in MATLAB (Mathworks, Natick, MA, USA), the peak value of resonant current is acquired, and expressed as I_T1max,pu = max[i′_T1,pu(t)]/n₁₃.

Figure 8 shows the peak value of resonant current I_T1max,pu, peak value of resonant capacitor voltage V_CR1max,pu and cutoff current of port 1 i_T1,pu(−ϕ₁₃/ω_s) versus P_1,pu under varying L_P. In the designing process, P₁ = 1000 W, P_B = P₃ = 1500 W, therefore, the maximum value of P_1,pu is 0.67.

Figure 8 indicates that the peak value of resonant current, peak value of resonant capacitor voltage and cutoff current increase L_P increases. From the point of view of reducing the power loss of proposed MR-TP-BDC, L_P should be chosen as small as possible. Meanwhile, the converter will lose its ZVS property when the cutoff current is very small. In this condition, the energy stored in the MR storage is not enough to get the output capacitor of metal-oxide-semiconductor field effect transistor (MOSFET) completely discharged. Therefore, the critical cutoff current value, which guarantee ZVS of converter, should be deduced.

The analysis above indicates that M₁ = M₂ = 1 are the optimal voltage gains to guarantee ZVS operation of all switches of proposed isolated MR-TP-BDC. Equation (14) shows the ZVS constraint expressions of three ports. While, the aforementioned conclusions are all based on ideal MOSFETs and the output capacitors of MOSFETs are neglected. However, in the actual experimental processes, the energy stored in the resonant tanks must be enough to get the output capacitors fully discharged during the dead time. Hence the cutoff current must be high enough to achieve ZVS condition.

When the MOSFETs are turned off, their drain-source voltages are equal to their respective port voltages. On the basis of the utilized design method, port 3 has the highest voltage of 400 V, and thus the output capacitors of MOSFETs in ports 3 store most energy in their cut-off stage. Besides, port 3 has the highest voltage, which means a smaller winding current. Hence the ZVS realization conditions of switches in port 3 are the most difficult. Moreover, the discharging current of the switch parasitic output capacitor of port 3 decreases when power is transferred from port 3 to port 1. Figure 9 shows the critical ZVS condition of switches in port 3 under the most severe situation. In this condition, output capacitor of S₉ is just completely discharged when the resonant current decreases to zero. The corresponding cutoff current is defined as I_tomin, which is the minimum cutoff current to guarantee ZVS operation of port 3.

In Figure 9, t₁–t₂ and t₃–t₄ are the dead time of port 3. At t₃, S₁₀ is turned off, and the output capacitors of S₉ and S₁₀ begin to get discharged and charged, respectively. The values of charging and discharging current of S₉ and S₁₀ are all i_T3,pu(t)/2. During t₃–t₄, i_T3,pu(t) is assumed to be decrease linearly. According to the discharging formula of capacitor, the voltage changing process of S₉ can be expressed as:

$$v_{\mathrm{DS}9}(t_4)-v_{\mathrm{DS}9}(t_3)=-\frac{1}{2C_{\mathrm{oss}}}{\displaystyle {\int }_{t_3}^{t_4}{i}_{\mathrm{T}3,\mathrm{pu}}(t)dt}$$

(21)

Thus, the critical ZVS condition of S₉ shown in Figure 9 is derived as:

$$V_3=\frac{1}{2C_{\mathrm{oss}}}\times \frac{1}{2}{I}_{\mathrm{tomin}}\times t_{\mathrm{DB}}$$

(22)

where C_oss is the parasitic output capacitor of switches and t_DB represents the dead time. For the MOSFET selected in this article, the value of parasitic output capacitor under 0–400 V voltage range is 150 pF. The dead time is chosen as 200 nS. By substituting C_oss and t_DB into (22), I_tomin is derived as 1.2 A. Since the power distribution among three ports are: P₁:P₂:P₃ = 2:1:3, then the minimum cutoff current assigned to port 1 is approximated as:

$$I_{\mathrm{tomin}1,\mathrm{pu}}= \frac{2}{3n_{13}}\frac{I_{\mathrm{tomin}}}{I_{\mathrm{B}}}=0.425$$

(23)

To ensure the converter efficiency under rated power state, the cutoff current should be minimized on the premise of realizing ZVS. Figure 8c shows that, when L_P = 10 μH, the cutoff current of port 1 is i_T1,pu(–ϕ₁₃/ω_s) = 0.40 and it doesn’t satisfy the ZVS constraint shown in (23). When L_P = 15 μH, i_T1,pu(–ϕ₁₃/ω_s) = 0.59, ZVS operation can be guaranteed. What’s more, the peak value of resonant current and resonant capacitor voltage are I_T1max,pu = 2.18 and V_CR1max,pu = 0.37 respectively, and both of them are in a reasonable range. To sum up, L_P = 15 μH is selected in the proposed isolated MR-TP-BDC.

4.3. Driving Frequency Optimization

Equation (6) indicates that the MR storage impedances under fundamental and third order frequencies change under varying F. The operating characteristics of the proposed converter should be compared under different F. The peak value of resonant current I_T1max,pu, peak value of resonant capacitor voltage V_CR1max,pu and cutoff current of port 1 i_T1,pu(–ϕ₁₃/ω_s) are plotted by MATLAB and are shown in Figure 10.

Figure 10 shows that the effects of F on I_T1max,pu and V_CR1max,pu are small and can be neglected. While the cutoff current i_T1,pu(–ϕ₁₃/ω_s) increases obviously with the increase of F. The ZVS constraint deduced in 4.2 is also shown in Figure 10c. If F = 1.15 is adopted in the full load range, ZVS properties will be missed. Therefore, to ensure optimal efficiency under full load range, driving frequency should increase with the decrease of power level. Values of F under the rated and half load conditions are selected as 1.15 and 1.35, respectively.

5. Experimental Results

To verify the feasibility of the proposed topology and the accuracy of the theoretical analysis, a 1.5 kW prototype is built and tested in the laboratory. The MOSFETs adopted in the system is C3M0065090D manufactured by CREE (Durham, NC, USA). The DSP TMS320F28379D from Texas Instruments (Dallas, TX, USA) is employed as the digital controller. The optimized parameters of the proposed converter are selected and shown in

Table 1. Parameters of the proposed system.

Converter Parameter	Value
Port 1 voltage/power	200 V/1000 W
Port 2 voltage/power	160 V/500 W
Port 3 voltage/power	400 V/1500 W
Transformer turns ratio n13:n23:1	0.5:0.4:1
Series resonant inductor LR	16 μH
Notch resonant inductor LP	15 μH
Series resonant capacitor CR	80 nF
Notch resonant capacitor CP	48 nF
Resonant frequency fr	95 kHz
Driving frequency fs	110~130 kHz

. In the experiments P₁, P₂ and P₃ are defined as positive when power flows from port 1 and port 2 to port 3, and vice versa.

5.1. Forward Operating Mode

Experimental results under rated and half load positive conditions are evaluated. In the rated positive mode, port 1 and 2 are connected to voltage sources of 200 V and 160 V, respectively. A resistive load of 106 Ω is connected to port 3. In this experiment, power flows from port 1 and 2 to port 3, v_T1 and v_T2 lead v_T3. The specific data of this experiment are given as follows: input voltage V₁ = 200 V, V₂ = 160 V; output voltage V₃ = 398 V; driving frequency f_s = 110 kHz, ϕ₁₃ = 14.2°, ϕ₂₃ = 11.1°; P₁ = 1015 W, P₂ = 497 W, P₃ = 1455 W. The efficiency is 96.2%.

Waveforms of output voltage and current of port 3 are shown in Figure 11a. i_T1, i_T2 and i_T3 are currents of three transformer windings and are presented in Figure 11b. Figure 12a–d show the operating waveforms of port 1, such as i_T1, and the drain-source voltages and the driving signals of S₁ and S₃ v_{DS_S1}, v_{G_S1}, v_{DS_S3} and v_{G_S3}. Figure 12e–h and Figure 12i–l show waveforms of port 2 and port 3 respectively. Figure 12b,d,f,h,j,l are zoomed-in versions of Figure 12a,c,e,g,i,k. It can be obtained from the zoom-in figures that the drain-source voltages of MOSFETs decrease to zero before their driving signals turn to positive. Furthermore, v_{G_S1} and v_{G_S5} turn positive when i_T1 and i_T2 are negative, v_{G_S3} and v_{G_S7} turn positive when i_T1 and i_T2 are positive. v_{G_S9} turns positive when i_T3 is positive, and v_{G_S11} turns positive when i_T3 is negative. The above-mentioned facts prove that S₁ and S₃ of port 1, S₅ and S₇ of port 2 and S₉ and S₁₁ realize ZVS successfully, which means all the three-port switches achieve the desirable ZVS feature.

Figure 13 and Figure 14 show waveforms under half load positive mode. In this condition, voltage sources of 200 V and 160 V are supplied to port 1 and port 2, respectively. The load resistance connected to port 3 is 213 Ω. In this experiment, output voltage V₃ = 399V; driving frequency f_s = 130 kHz, ϕ₁₃ = 15.8°, ϕ₂₃ = 10.3°; P₁ = 549 W, P₂ = 230 W, P₃ = 747 W; the efficiency is 95.8%.

Waveforms of output voltage and current of port 3 are shown in Figure 13a. Figure 13b shows waveforms of three transformer windings. Figure 14a,b, Figure 14c,d and Figure 14e,f demonstrate waveforms of port 1, port 2 and port 3. Like the experimental results shown in Figure 12, ZVS is achieved for all switches of the three ports.

5.2. Reverse Operating Mode

In the negative operating mode, 400 V voltage source is supplied to port 3 and resistive loads are connected to port 1 and port 2. Power is transferred from port 3 to port 1 and port 2, and both ϕ₁₃ and ϕ₂₃ are negative. Experimental results under rated and half load conditions are illustrated.

Under the rated power condition, resistances of port 1 and port 2 are 40 Ω and 50 Ω, respectively. The experimental results are listed as: output voltages V₁ = 198 V, V₂ = 159 V; driving frequency f_s = 110 kHz, ϕ₁₃ = −13.9°, ϕ₂₃ = −11.4°; P₁ = −965 W, P₂ = −502 W, P₃ = −1520 W; efficiency is 96.5%.

Figure 15a gives the waveforms of output voltage and current of port 1 and 2. Figure 15b shows the waveforms of resonant currents of three ports.

Figure 16a demonstrates i_T1, v_{DS_S1} and v_{G_S1} of port 1. Figure 16c illustrates i_T2, v_{DS_S5} and v_{G_S5} of port 2. Figure 16e shows i_T3, v_{DS_S9} and v_{G_S9} of port 3. Figure 16b,d,f are zoomed-in waveforms of Figure 16a,c,e. The waveforms of three ports are consistent with the analysis above, and ZVS is achieved for all MOSFETs of the three ports.

Under the half power condition, resistances of port 1 and port 2 are 80 Ω and 100 Ω, respectively. The experimental results are listed as: output voltages V₁ = 197 V, V₂ = 159 V; driving frequency f_s = 130 kHz, ϕ₁₃ = −15.0°, ϕ₂₃ = −11.3°; P₁ = −484 W, P₂ = −250 W, P₃ = −764 W; efficiency is 96.0%.

Waveforms of output voltage and current of port 1 and 2 are shown in Figure 17a. Figure 17b shows the waveforms of three transformer windings. The waveforms illustrated in Figure 18 are same those in Figure 16. ZVS is achieved for all the MOSFETs.

The comparisons of phase shift angles obtained from theoretical calculation and experiment are given in

Table 2. Comparison of phase shift angles from theoretical calculation and experiment.

Power Level	Method	ϕ13	ϕ23
Positive 100% (1500 W)	Theory	12.5°	9.7°
	Experiment	14.2°	11.1°
Positive 50% (750 W)	Theory	14.6°	11.2°
	Experiment	15.8°	10.3°
Negative 100% (1500 W)	Theory	−12.5°	−9.7°
	Experiment	−13.9°	−11.4°
Negative 50% (750 W)	Theory	−14.6°	−11.2°
	Experiment	−15.0°	−11.3°

. It can be seen that all the values match reasonably close to each other, and this proves the accuracy of the theoretical analysis.

Finally, the measured efficiency curves under positive and negative conditions is shown in Figure 19. The efficiency under rated bidirectional conditions are 96.2% and 96.5%, respectively. The highest efficiency under forward condition is 96.7% at 1.25 kW, and 96.9% under 1 kW in reverse mode. Furthermore, when the power is above 0.5 kW, the efficiencies of both directions are higher than 95.5%. The proposed converter is proved to have high efficiency within entire load range.

6. Conclusions

In this paper, a three-port LCLC multi-resonant bidirectional DC-DC converter is developed. Through parameter design, the LCLC possesses two SRFs (f_r and 3f_r) and a NRF (2f_r). Hence, the energy of first and third orders can be delivered through the MR tank, and circulating energy of the resonant tanks is reduced. What’s more, by adjusting the driving frequency under different load conditions, ZVS characteristics for all three-port switches are guaranteed among entire load range. Besides, a design procedure with normalized variables is presented. At last, a 1.5 kW prototype is implemented to validate the feasibility and practicability of the proposed converter. Experimental results indicate that the proposed converter presents high efficiency within whole load range. When the power is above 0.5 kW, the bidirectional efficiencies maintains as high as over 95.5%, and the highest efficiencies under forward and reverse conditions are 96.7% and 96.9% respectively.