TSPEM Parameter Extraction Method and Its Applications in the Modeling of Planar Schottky Diode in THz Band

Abstract

In this paper, a new method for the parameter extraction of Schottky barrier diode (SBD) is presented to eliminate the influence of parasitic parameters on the intrinsic capacitance-voltage (C-V) characteristics of the Schottky diodes at high frequencies. The method is divided into the de-embedding and parameter extraction, including six auxiliary configurations and, is referred tos as Two-step Six-configuration Parameter Extraction Method (TSPEM). Compared to the traditional junction capacitance extraction method, this method can extract the value of junction capacitance at higher frequencies with higher accuracy. At the same time, compared to the other de-embedding methods, this method shows better performance in de-embedding the contributions of parasitic structures from the transmission line measurements. The intrinsic junction capacitances obtained by this method and the three-dimensional (3-D) electromagnetic model are combined to form a diode simulation model, which accurately characterizes the capacitance characteristics of the SBD. It was verified with a 200 GHz double frequency multiplier, and the simulation results and measurement results showed good consistency.

1. Introduction

The development of terahertz applications, such as astrophysics, earth science, imaging, and communication, has generated an increasing demand for terahertz solid-state sources [1,2,3]. The terahertz solid-state source is extremely dependent on the terahertz frequency multiplier. The SBD is the core solid-state device of the terahertz frequency multiplier [3,4]. The terahertz frequency multiplier uses the nonlinear variable capacitance characteristic of the SBD to obtain the generation of multiplier frequency components. As the working frequency increases, the requirements for the accuracy of the SBD variable capacitor model during the design of the terahertz frequency multiplier also increases accordingly. The key to improving the accuracy of the model is by finding a method to accurately characterize the intrinsic junction capacitance characteristics of the SBD.

In the current terahertz frequency doubling circuit design, the commonly used diode model is a physics-based numerical model, also known as the 3-D EM model [5]. The 3-D EM model utilizes a complete electromagnetic analysis method based on Maxwell’s equations to characterize the high-frequency parasitic effects caused by the complex passive structure around the Schottky junction. The diode SPICE model is used for characterizing the intrinsic nonlinear capacitance behavior of the diode. As shown in Figure 1, a miniature coaxial probe is precisely inserted at each position of the Schottky junction, and a wave port is allocated at the end of the coaxial probe for connecting the diode SPICE model [6,7,8]. The parasitic effects are imported in the form of a scatter matrix into the Agilent Advanced Design System (ADS) for further combining with the intrinsic model of a diode to predict the nonlinear capacitance behavior of the diode. This method has become a general modeling technique for SBDs and is widely used in the design of terahertz Schottky diode multipliers [9,10,11,12,13,14,15], mixers [16,17,18,19], and detectors [20,21].

The electromagnetic model obtained through the method of complete electromagnetic analysis based on Maxwell’s equations could effectively characterize the high-frequency parasitic effects. Accurately obtaining the diode intrinsic nonlinear capacitance behavior is an important factor in the accuracy of the 3-D EM model. In the design of the terahertz hybrid integrated circuits, the zero-bias junction capacitance combined with the diode varactor formula is used for generating the varactor characteristics [13,15]. This method uses the variable capacitance formula under the DC condition, which cannot accurately characterize the C-V characteristics of the diode under high frequencies. In the process of Terahertz monolithic integrated circuit (TMIC) design, the C-V characteristics measured by the semiconductor parameter analyzer provide the data basis for obtaining the intrinsic nonlinear capacitance behavior of the diode [22,23]. The semiconductor parameter analyzer can only obtain the total capacitance of the diode structure along with the test structure and cannot accurately characterize the intrinsic junction capacitance of the diode.

The physical size of the device is smaller than the value of accuracy of the on-chip test probe; thus, the test pads and the interconnects are required to access the device under test (DUT) (Figure 2). In the small-signal S-parameter testing, these test pads and interconnects introduce additional effects. The measurement results cannot accurately characterize the small-signal characteristics of the device, although there are on-chip test de-embedding methods that could reduce the impact of the test results to a certain extent [24,25,26]. As the frequency increases, the test pad and the transmission structure cannot simply be equivalent to the ground capacitance and ideal transmission line, respectively. This makes the errors of the parasitic effects from the test pad, and those of the interconnects, more prominent. An accurate de-embedding method is therefore required to eliminate these parasitic contributions.

In this paper, a new method is developed, named the Two-step Six-configuration Parameter Extraction Method (TSPEM). This method is divided into two parts: The peripheral structure de-embedding and parameter extraction. During the peripheral structure de-embedding step, the effect of the peripheral test structure is de-embedded by calculating the scattering matrix. In the parameter extraction step, the effect of the parasitic parameters of the diode is extracted and removed through four auxiliary configurations, and finally, the accurate value of the intrinsic junction capacitance is obtained. The TSPEM possesses the characteristics of high precision and simplicity, and it shows a better performance in de-embedding the contributions of the parasitic structures from the transmission line measurements and can extract the intrinsic junction capacitance value more accurately at a higher frequency. Later, the accuracy of the method was verified through electromagnetic simulation and the on-chip measurement results. A 180–220 GHz doubler was built to verify the accuracy of the model built using the TSPEM.

2. Methods

The TFPEM method aims to obtain the precise value of the junction capacitance at high frequencies by using the matrix de-embedding algorithm and the equivalent circuit parameter extraction method. The first step is to de-embed the test results at both ends of the device by two de-embedding auxiliary configurations. The second step is to accurately obtain the value of the junction capacitance by the four parameters of the extraction auxiliary configurations.

2.1. Peripheral Structure De-Embedding

This method realizes the de-embedding of the test results through the transmission matrix operation of the cascade system. It also reduces the impact error caused by the discontinuity when the test pads and transmission structure are directly equivalent to capacitors and an ideal transmission line. Figure 2 reveals that the transmission matrix of either of the test structures can be decomposed into a cascade of five two-port networks. The network comprises test pads, the transmission lines and associated pad-line discontinuities, and the intrinsic device.

The pads and transmission lines can be concentrated in a single two-port network without losing generality. Equivalent representations of the test on-chip structure of the device are simplified, as shown in Figure 3. Consequently, the (ABCD) transmission matrix of the test on-chip structure of the device can be represented by the following formula:

$$A_{DUT}^t=A_{L-trans} ·A_{DUT\prime } ·A_{R-trans}$$

(1)

where $A_{L-trans}$ is a two-port network formed by the cascading left transmission line and the left pad. Left $A_{R-trans}$ is a two-port network formed by the cascading right transmission line and the right pad. $A_{DUT}$ is a hybrid structure composed of the DUT and the electrical coupling between the left and right transmission structures. $A_{DUT\prime }$ can be expressed as:

$$A_{DUT\prime }={\left[A_{L-trans}\right]}^{-1}·A_{DUT}^t·{\left[ A_{R-trans}\right]}^{-1}$$

(2)

Like the on-chip test, the open pad structure can also be expressed as:

$$A_{ce}={\left[A_{L-trans}\right]}^{-1}·A_{pad-open}^t·{\left[ A_{R-trans}\right]}^{-1}$$

(3)

$A_{L-trans}$ and $A_{R-trans}$ can be obtained by de-embedding the auxiliary “pad-through” configuration. Since the interaction is very small, the direct interaction between the two transmission structures is not considered. $A_{pad-thr}^t$ can be represented by two mirrored cascading T-shaped networks, as shown in Figure 4. One single transmission structure is modeled as one shunt impedance and two series impedances, respectively. $A_{pad-thr}^t$ can be expressed as:

$$\begin{gathered} A_{pad-thr}^t=A_{L-trans} ·A_{R-trans}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em} \\ =\left[\begin{array}{cc}1+Z_1{Y}_3& Z_1{Z}_2{Y}_3+Z_1+Z_2\\ Y_3& 1+Z_2{Y}_3\end{array}\right] \\ ·\left[\begin{array}{cc}1+Z_2{Y}_3& Y_3\\ Z_1{Z}_2{Y}_3+Z_1+Z_2& 1+Z_1{Y}_3\end{array}\right] \end{gathered}$$

(4)

Later, we have the transmission matrix of the two transmission structures:

$$\begin{gathered} A_{L-trans}=swap\left(A_{R-trans}\right)\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em} \\ =\left[\begin{array}{cc}k& A_{12pad-thr}^t/\left(2·k\right)\\ k·A_{21pad-thr}^t/2·k\left(1+\left(A_{11pad-thr}^t+A_{11pad-thr}^t\right)/2\right)& \left(1+\left(A_{11pad-thr}^t+A_{11pad-thr}^t\right)/2\right)/\left(2·k\right)\end{array}\right] \end{gathered}$$

(5)

The hybrid structure DUT’can be expressed in terms of the Y-parameters as a parallel combination of the DUT and the electrical coupling between the left and right transmission structures. The effects of electrical coupling can be canceled out, and the DUT can be expressed as:

$$Y_{DUT}=Y_{DUT\prime }-Y_{ce}$$

(6)

2.2. Parasitic Research

After obtaining the transfer matrix de-embedded to both ends of the device, the research process of the SBD parasitic characteristics is explained. The equivalent circuit was built based on the particular structure of the SBD. The coupling field between both pads and the finger-to-pad coupling are modeled as C_pp and C_fp. The air-bridge finger is modeled as self-inductance (L_f) and the series resistance (R_f) in the series structure. The equivalent circuit is shown in Figure 5. The parasitic inductance of the cathode and anode two mesas L_{pad <<} L_f, which can be neglected. Z_branch is the equivalent circuit of the diode metal finger and junction branch, which ignores the influence of mesa parasites. Z_intrinsic represents the intrinsic part of the diode, which is composed of intrinsic junction capacitance (C_j) and junction resistance (R_j) in parallel, where the junction capacitance can be described as:

$$C_j=\gamma \epsilon \frac{A_a}{\sqrt{\frac{2\epsilon }{q{N}_D}\left(V_{bi}-V\right)}}$$

(7)

where $\gamma$ is the edge effect correction factor, N_D is the doping concentration, V_bi is the built-in potential difference, and A_a is the junction area.

The value of these parasitic parameters can be found by the second step of the TFPEM method, and then, the value of the junction capacitance can be obtained. The possible steps for parameter research are shown in the flow diagram shown in Figure 6. First, the value of the parasitic parameter is extracted through the four extraction configurations. Then, the value of the intrinsic junction capacitance is obtained by bringing the value of the parasitic parameter obtained into the equivalent circuit in Figure 5b. In this step, four extraction configurations are used, namely, the diode-open, diode-short, pin-open, and pin-short. The detailed information of the configuration is illustrated by the corresponding simulation model, which is shown in Figure 7. The diode-open structure is a diode structure without a metal finger. The diode-short structure is a diode structure in which the metal finger directly connects the cathode and the anode. The pin-open structure is a diode structure without Schottky contact. The pin-short structure is a diode structure in which ohmic contact is achieved at the Schottky junction through high work function metal and annealing.

2.2.1. Step 1—Parasitic Capacitance Extraction

The high-frequency electromagnetic coupling brought about by the diode geometry is mainly reflected in the parasitic capacitances. For a high-frequency planar diode, the capacitances range within a tenth to tens of a femtofarad. Thus, the parasitic capacitors are extracted at a relatively low-frequency range, e.g., the lower gigahertz frequency range. In this frequency band, the diode capacitances are dominant compared to parasitic inductances and resistances. With this, the influence of parasitic inductance and resistance can be neglected in the process of capacitor extraction. The diode C_pp and C_fp is estimated from the diode-open, pin-open, and extraction auxiliary configurations. Since the equivalent circuit is reciprocal, the parasitic capacitances are calculated as per the following assumptions (8) and (9).

$$C_{pp}=\frac{Im\left(-Y_{D\_O}^{\mathrm{de}-\mathrm{emb}}\left(2,1\right)\right)}{\omega }$$

(8)

$$C_{pf}=\frac{Im\left(Y_{D\_O}^{\mathrm{de}-\mathrm{emb}}\left(2,1\right)-Y_{P\_O}^{\mathrm{de}-\mathrm{emb}}\left(2,1\right)\right)}{\omega }$$

(9)

2.2.2. Step 2—Parasitic Resistance Extraction

In general, the series resistance for a surface-channel planar Schottky diode is composed of an air-bridge finger resistance R_finger, top junction epi-layer resistance R_epi, buffer-layer spreading resistance R_spreading, and ohmic-contact resistance R_contact. Among them, the R_epi, R_spreading, and R_contact constitute the series resistor R_s formed by the cathode mesa of the diode, as stated in (1). In this paper, an ideal conductor is assumed, and other series resistance components are ignored (i.e., treated as perfect electric conductors).

$$R_s=R_{\mathrm{epi}}+R_{\mathrm{spreading}}+R_{\mathrm{contact}}$$

(10)

The diode resistance is calculated with pad-open, pad-short, and pin-short auxiliary configurations. Compared to the DC method, the resistance obtained by this method is more realistic under high-frequency conditions.

$$R_s=Re\left(Z_{P\_S}^{\mathrm{de}-\mathrm{emb}}\left(2,1\right)-Z_{D\_S}^{\mathrm{de}-\mathrm{emb}}\left(2,1\right)\right)$$

(11)

$$Y^{\mathrm{de}-\mathrm{emb}}-Y_{D\_O}^{\mathrm{de}-\mathrm{emb}}=\frac{1}{R_{\mathrm{S}}\left[\begin{array}{cc}1& 1\\ 1& 1\end{array}\right]+Z^{branch}}$$

(12)

$$R_{\mathrm{finger}}=Re\left(\frac{1}{Y_{D\_S}^{branch}\left(2,1\right)-Y_{D\_P}^{branch}\left(2,1\right)}\right)$$

(13)

2.2.3. Step 3—Parasitic Inductance Extraction

The parasitic inductance of planar Schottky diodes is mainly derived from metal fingers. The inductance resides within the range of several to tens of pico-Henrys. In the traditional extraction method, the parasitic inductances are extracted at high frequencies, for instance, ranges of hundreds of gigahertz, which raises the requirements for the test system. Here, we use pad-open and pad-shirt auxiliary configurations to extract the value of the parasitic inductance.

$$L_{\mathrm{f}}=\frac{Im\left(1/\left(Y_{D\_S}^{branch}\left(2,1\right)-Y_{D\_P}^{branch}\left(2,1\right)\right)\right)}{\omega }$$

(14)

2.2.4. Step 4 —Intrinsic Parameter Extraction

The junction capacitance of the planar Schottky diode comes from the space charge region formed by the Schottky contact. The capacitance-voltage (C-V) characteristics of the SBD can be measured by using the semiconductor parameter analyzer. However, the capacitance obtained by the measurement method is the total capacitance of the SBD. The total capacitance consists of the intrinsic junction capacitance (C_j), finger-to-pad capacitance (C_fp), and the pad-to-pad capacitance (C_pp). However, it cannot be simply expressed as the sum of capacitances. By bringing the parasitic parameters obtained in the first three steps into the model, as shown in Figure 5b, and by eliminating their influence, the value of the SBD intrinsic junction capacitance can be obtained through parameter fitting through engineering. At the same time, the analytical expression of junction capacitance is also given. Its numerical calculation formula is provided as follows.

$$C_{\mathrm{j}0}=\frac{Im\left(1/(1/Y_{DUT}^{branch}\left(2,1\right)-1/Y_{D\_S}^{branch}\left(2,1\right))-1/(1/Y_{P\_O}^{branch}\left(2,1\right)-1/Y_{D\_S}^{branch}\left(2,1\right))\right)}{\omega }$$

(15)

3. Results and Discussion

The effectiveness of this de-embedding method is verified through the three-dimensional electromagnetic simulation results, in which the 3-D electromagnetic models of the structure of the parameter extraction parts are built. The ports of the 3-D electromagnetic model are directly set on the edges of both sides of the anode and cathode. This model is used for accurately characterizing the electromagnetic characteristics of the parasitic parameter extraction structure. Three-dimensional models of the parasitic parameter extraction structure under test and the de-embedded structures are also built, in which the wave ports are set at the two edges of the CPW transmission structure, which is the same as the measurement structure. This model is used for simulating the result of the on-chip measurement of the parasitic parameter extraction structures and a de-embedded structure. The electromagnetic simulation results of the above structure in the 3-D electromagnetic simulation software are exported in the form of the S-parameter files. The electromagnetic characteristics of the parasitic test structure are de-embedded by the matrix operations.

Figure 8 shows the comparison between the S-parameters before and after the de-embedding of the parasitic test structures along with the S-parameters of the parasitic de-embedding structure. It can be seen that the de-embedding method mentioned in this paper is more accurate at higher frequencies compared to the other methods (L–2L method [25], L1–L2 method [26]). This de-embedding method can effectively remove the influence of the parasitic parameter caused by the test pads and the transmission line during the SBD parameter extraction process.

A series of GaAs SBD were produced with different Schottky junction diameters, de-embedding structures, and parasitic parameter extraction structures. The diameters of this series of diodes are 2 μm, 3 μm, 4 μm, and 5 μm. Apart from the Schottky junction diameter, the structure and physical dimensions of the SBD are the same in this series of diodes, which makes it have the same parasitic parameters but different junction capacitance values. Since the parasitic parameters do not change with the bias voltage, we tested the electromagnetic coupling characteristics of the de-embedding structures and the parasitic parameter extraction structures with the bias voltage (V_bias) = 0 V. The intrinsic junction capacitance (C_j0) and the parasitic parameters included the pad-to-pad capacitance (C_pp), finger-to-pad capacitance (C_fp), finger inductance (L_f), finger resistance (R_f), and the cathode series resistance (R_s). The extraction results of these parasitic parameters are shown in

Table 1. Intrinsic and parasitic parameters of the diodes.

Parameters	Value
Intrinsic junction capacitance, Cj0	5.9 fF (2 μm), 11.7 fF (3 μm), 20.0 fF (4 μm), 31.6 fF (5 μm)
pad to pad capacitance, Cpp	7.2 fF
finger to pad capacitance, Cfp	2.7 fF
finger inductance, Lf	35.5 pH
finger resistance, Rf	0.25 Ω
cathode series resistance, Rs	6.51 Ω (2 μm), 6.14Ω (3 μm), 5.41 Ω (4 μm), 5.05 Ω (5 μm)

. These parameters help better guide the design of the physical structure of the diode.

We bring the C-V characteristics obtained by three different junction capacitance extraction methods into the model shown in Figure 1 to obtain a three-dimensional simulation model of the diode. In Method 1, the C-V characteristic of the diode junction capacitance is obtained through TFPEM. In Method 2, The C-V characteristic of the diode is measured by a semiconductor analyzer. In Method 3, the I-V test result of the diode is used to obtain the value of the thickness of the Schottky junction depletion layer, and then the junction capacitance is equivalent to the traditional formula of parallel plate capacitance to obtain the C-V characteristic of the diode as shown in Equation (7). The formula for the capacitance obtained in Method 3 is as follows. Figure 9 shows the comparison between the electromagnetic characteristics of the three diode models and the measured results. It can be seen that the model established by the C-V characteristics obtained by the TFPEM showed very good consistency with the test results. The variable capacitance characteristics of the device are well characterized in the model. The model established by the C-V characteristics obtained by the semiconductor analyzer at a frequency of 1 MHz showed a greater coupling effect because the influence of the parasitic parameters was not eliminated. The model established by the I-V extraction method and the C-V characteristic obtained by the traditional formula [27] showed a greater varactor characteristic because of the inability to correct the built-in voltage. The accuracy of this method is evaluated by computing the errors between the S-parameters for the device-under-test (DUT) and the extracted model. The frequency and voltage-dependent error function is written as:

$$e\left(V\right)=\frac{1}{4}{\sum }_{i=1}^2{\sum }_{j=1}^2\frac{{\left|S_{ij}^{DUT}\left(V\right)-S_{ij}^{mod}\left(V\right)\right|}^2}{{\left(S_{ij}^{DUT}\left(V\right)\right)}^2}$$

(16)

where $S_{ij}^{DUT}\left(V,{\omega }_k\right)$ and $S_{ij}^{mod}\left(V,{\omega }_k\right)$ are the measurement and three model S-parameters at different voltage points, respectively. The average error, $\overline{e}$ is defined as:

$$\overline{e}=\frac{1}{N}{\sum }_{n=1}^{N}e\left(V\right)$$

(17)

The average errors of the TFPEM model, the formula-based model, and the C-V measurement are 0.0011, 0.0173, and 0.1168, respectively. There is more remarkable agreement between the characteristics obtained by the method proposed in this paper and the measured results compared to other methods.

4. Application

To further verify the accuracy of the model, a 200 GHz TMIC doubler circuit was simulated based on this model, and the simulation results were compared with the measured results for verification [13]. The measurement was carried out under low-power conditions, eliminating the error caused by the increase in reverse leakage during high-power conditions. The cavity of the designed doubler was made of brass material, and the entire surface was gold-plated. The measurement setup employed for testing the frequency doubler MMICs is presented in Figure 10. Here, an analog signal generator followed by a W-band, active × 8 frequency multiplier was utilized to generate an input signal in the 86–106 GHz band with a typical output power of +10 dBm. The output power of the frequency multipliers was measured using a PM4 power meter. In addition, a Sub-Miniature version A (SMA) coaxial RF connector was connected to the main transmission circuit using gold wire bonding, and a low forward bias (+0.8 V) was applied to the SMA port to bias the SBDs in the TMIC doubler.

The TFPEM model simulation and the measured output power of the TMIC doubler are shown in Figure 11, which concern the frequency along with the input power. The measured output power of the TMIC doubler was greater than 5.0 mW within the range of 188 GHz to 212 GHz, and the maximum output power was about 13.35 mW at 200 GHz. The efficiency of the TMIC doubler was greater than 8% within the range of 182 GHz to 218 GHz except for individual frequency, and the maximum efficiency was 12.6% at 185 GHz. The center frequency and bandwidth of the TFPEM model simulation results were consistent with the measurement results compared with the formula-based model simulation results. The minimum point around 207 GHz was better reflected in the TFPEM model simulation results. The difference in output power was mainly caused due to the introduction of resistance during assembly.

5. Conclusions

In this paper, the TSPEM method was developed to get a more accurate intrinsic junction capacitance value of the SBD in the Terahertz band. In the peripheral structure de-embedding step, the effect of the peripheral test structure is de-embedded by calculating the scattering matrix. In the parameter extraction step, the effect of the diode parasitic parameters is extracted and removed through four auxiliary configurations, and finally, the accurate value of the intrinsic junction capacitance is obtained. The accuracy of the de-embedding step and parameter extraction step of the TFPEM method was evaluated through three-dimensional electromagnetic simulation and diode on-chip measurement, respectively. The accuracy of this method was further verified by the performance of a 200 GHz double frequency converter. This method shows more accurate high-frequency characteristics and provides a more accurate simulation model for the future designs of the TMIC circuit.