Abstract: In recent year as the complexity of Integrated circuits increases the physical design complexity also increases. As the technology advances the Integrated circuits are expected to be low area as possible. To reduce area of total chip, we use some efficient algorithms for floorplan. A floorplan optimization is usually about placing all modules inside a partition so that the total area of block should be less as possible, to get the solution for this NP hard problem we use some meta-heuristic algorithms such as Simulated annealing(SA), Particle swarm optimization(PSO), Ant colony optimization(ACO), Genetic algorithm(GA) etc.