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High speed multiplier design using Decomposition Logic

Ramanathan Palaniappan (Department of Electrical and Engineering, University of Bechar, Algeria)
Vanathi Thangapandian Ponnisamy (Department of Electrical and Engineering, University of Bechar, Algeria)
Agarwal Sundeepkumar (Department of Electrical and Engineering, University of Bechar, Algeria)

The multiplier forms the core of a Digital Signal Processor and is a major source of power dissipation. Often, the multiplier forms the limiting factor for the maximum speed of operation of a Digital Signal Processor. Due to continuing integrating intensity and the growing needs of portable devices, low-power, high-performance design is of prime importance. A new technique of implementing a multiplier circuit using Decomposition Logic is proposed here which improves speed with very little increase in power dissipation when compared to tree structured Dadda multipliers. Tanner EDA was used for simulation in the TSMC 180nm technology.

Keywords: Digital Signal Processor, Dadda multiplier, Decomposition Logic