This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL) for high speed serial-communication links. These research results are used for the LpGBT (Low Power Gigabit Transceiver) chip which will be widely used for optical data-links between the detectors and the counting rooms in the HL LHC experiments. The PLL features a novel LC-oscillator architecture which is not sensitive to single-event transients. Additionally, the circuit uses triple-modular redundancy and is designed in a 65 nm CMOS technology.