An FPGA Implementation of a HOG-based Object Detection Processor

Kosuke Mizuno; Yosuke Terachi; Kenta Takagi; Shintaro Izumi; Hiroshi Kawaguchi; Masahiko Yoshimoto

doi:10.2197/ipsjtsldm.6.42

Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

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Keywords: image recognition, histograms of oriented gradients, support vector machine, hardware implementation

JOURNAL FREE ACCESS

2013 Volume 6 Pages 42-51

DOI https://doi.org/10.2197/ipsjtsldm.6.42

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Abstract

This paper describes a Histogram of Oriented Gradients (HOG)-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40MHz for SVGA resolution video (800 × 600pixels) at 72 frames per second (fps).

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