A 14b, twofold time-interleaved incremental delta sigma ADC using hardware sharing

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TCASI9153145.pdf (3.52 MB)

Date

2020-07-30

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Publication Type

Wissenschaftlicher Artikel

DOI

http://dx.doi.org/10.18725/OPARU-36942

Published in

IEEE Transactions on Circuits and Systems I: Regular Papers, 2020

Abstract

High-resolution, single-loop incremental DeltaSigma (I-ΔΣ) ADCs require large oversampling ratios to sufficiently suppress quantization noise. This limits the bandwidth of most designs to the low-kHz range. To overcome this problem, the presented proof-of-concept design makes use of time interleaving two third-order I-ΔΣ modulators with embedded hardware sharing that helps to enhance the efficiency of the presented modulator. The modulator is fully reconfigurable in a way that both channels can either be operated time interleaved or independent from each other. This is a means of enhancing the flexibility and efficiency of the modulator depending on the application scenario. The presented design was fabricated in a 180nm technology node.

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Faculties

Fakultät für Ingenieurwissenschaften, Informatik und Psychologie

Institutions

Institut für Mikroelektronik

Citation

DFG Project uulm

Keywords

Clocks, Quantization (signal), Bandwidth, Incremental ADC, incremental &#916, time interleaving, hardware sharing, Modulation, Übertragungsfunktion, Bandbreiteneffizienz, Sigma-Delta-Wandler, Modulator, Hardware, Attenuation (Physics), Transfer functions, Calibration, DDC 530 / Physics