Indian Journal of Science and Technology
DOI: 10.17485/ijst/2017/v10i4/110714
Year: 2017, Volume: 10, Issue: 4, Pages: 1-10
Original Article
S. Rekha1* and A. M. Bhavikatti2
1Visvesvaraya Technological University, Belagavi - 590018, Karnataka, India; [email protected] 2Department of CSE, Bheemanna Khandre Institute of Technology, Bhalki, Bidar - 585328, Karnataka, India; [email protected]
*Author for the correspondence:
S. Rekha
Visvesvaraya Technological University, Belagavi - 590018, Karnataka, India; [email protected]
Background/Objectives: Mainstream electronic designs are realized by System on Chip (SOC) that pushes the limits of integration. Network–On-Chip (NOC) for high speed is demanding in communication system to transfer data between transmitter (Tx) and receiver (Rx). NoC switch consists of Tx, Rx, Processing elements (PEs) and control circuits to process data. Methods: The PEs connected to a hub for communication topology through NoC switches which are mainly responsible for communication establishment of inter PEs communication channels. Novel NoC bit encoder and decoder transition (NOC BEDT) algorithmis used to optimize the hardware device utilization,speed and power consumption of communication system. The NoC BEDT consists of single switch,xored encoder with decoder. Findings: In existing work, each switch occupies lot of hardware as used in Field Programmable Gate Array (FPGA) and speed limited to 10Mbps. The experiments carried out of proposed NoC BEDT algorithm carried on real data and validation by Chipscope pro in Xlinx 13.4 DSP designsuite which showed 24% reduction in power consumption and 65% improvement in speed ofdata transmission of data rate upto 10 Gbps.
Keywords: BEDT, Encoder, Decoder, NoC, Routing, Switching, Topology, FPGA
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