Regular Section
Design and Implement of High Performance Crypto Coprocessor
2014 Volume E97.A Issue 4 Pages 989-990
Details
2014 Volume E97.A Issue 4 Pages 989-990
This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189MHz, outperforms the software-based SSL protocol.
