IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Circuit, System, and Computer Technologies
A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC
Muchen LIJinjia ZHOUDajiang ZHOUXiao PENGSatoshi GOTO
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2013 Volume E96.A Issue 6 Pages 1366-1375

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Abstract

As the successive video compression standard of H.264/AVC, High Efficiency Video Codec (HEVC) will play an important role in video coding area. In the deblocking filter part, HEVC inherits the basic property of H.264/AVC and gives some new features. Based on this variation, this paper introduces a novel dual-mode deblocking filter architecture which could support both of the HEVC and H.264/AVC standards. For HEVC standard, the proposed symmetric unified-cross unit (SUCU) based filtering scheme greatly reduces the design complexity. As a result, processing a 16×16 block needs 24 clock cycles. For H.264/AVC standard, it takes 48 clock cycles for a 16×16 macro-block (MB). In synthesis result, the proposed architecture occupies 41.6k equivalent gate count at frequency of 200MHz in SMIC 65nm library, which could satisfy the throughput requirement of super hi-vision (SHV) on 60fps. With filter reusing scheme, the universal design for the two standards saves 30% gate counts than the dedicated ones in filter part. In addition, the total power consumption could be reduced by 57.2% with skipping mode when the edges need not be filtered.

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© 2013 The Institute of Electronics, Information and Communication Engineers
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