Abstract
In this paper we present experimental and simulation results of the transient response of amorphous silicon (a-Si) thin film transistors (TFTs) over many orders of magnitude in time after the application of a voltage pulse to the gate. In general three regimes are observed by plotting drain current versus the logarithm of time. At times longer than the carrier transit time and extending up to 1–100 msecs, the current rapidly decreases due to trap filling, after which it then slowly decays up until defects are created in the silicon channel when it then finally decays more rapidly again. Our simulation results are in good agreement with the data for the short time trap filling regime, as a function of both gate bias and stress condition. Measurements at elevated temperatures show that the middle slow decay regime is caused by charge injection into interface states or the gate dielectric. Finally we also demonstrate that this slow decay regime does not occur in nin diodes, confirming that it is not caused by defect generation in the a-Si, and is instead related to the presence of the dielectric in a TFT.
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Acknowledgments
The work in this paper was primarily a collaboration between Peter LeComber and Morten Foss Willums at the University of Dundee, and myself, Mike Hack, and Richard Weisfield at Xerox PARC Throughout the last few years I have had the great privilege of both knowing and working with Peter LeComber. He was both a good friend and an excellent and stimulating colleague. He will be sorely missed by all of us here at PARC. The authors would also like to thank Warren Jackson for helpful discussions.
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Hack, M., Weisfield, R., Willums, M.F. et al. Transient and Stress Effects in Amorphous Silicon Thin-Film Transistors. MRS Online Proceedings Library 297, 865–870 (1993). https://doi.org/10.1557/PROC-297-865
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DOI: https://doi.org/10.1557/PROC-297-865