We proposed a new architecture for a phase-locked loop (PLL) obtained by comparing clock periods. We evaluated the use of a clock-period comparator (CPC) for the digitally controlled PLL we propose, where only the frequency should be locked. However, frequency control with the CPC resulted in the phase being locked. Thus, phase-lock operation was also achieved. The theoretical analysis of the phase-lock mechanism was confirmed through system simulations. We discussed about dead-zone problem caused by a time delay of circuits. We evaluated phase-shift direction detector to solve the dead zone problem. We designed the element blocks of the new PLL using a 0.25-μm CMOS process. We confirmed phase-lock operation through SPICE simulations of the MOSFET level. Moreover, we manufactured a trial circuit for the new PLL. We also confirmed phase-lock operation in the proposed PLL through measurements.