Power-Efficiency of Signal Processing Circuits in Implantable Multichannel Brain-Machine Interface
The nature of the neural signals, increasing density in multichannel arrays, information quality, and feasible data bandwidth pose significant challenges encountered in a power-efficient design of implantable brain-machine interface. In this paper, we propose a set of solutions to address
this design problem at both circuit- and system abstraction level. In particular, we review circuits for real time read-out of neural signals and discuss the role of classification in hardware neural processing architectures; we review the challenges of realizing power-efficient circuits in
physical systems and present examples of mixed-signal electronic circuits that implement them; we provide a broad view of optimization approaches, and their possible combination in effective complimentary techniques. We validate the approach with experimental results obtained from our own
circuits and systems, and argue how the circuits and systems presented in this work represent a valid set of components for power-efficient design of implantable multichannel brain-machine interface.
Keywords: BRAIN-MACHINE INTERFACE; NEURAL RECORDING INTERFACE; POWER OPTIMIZATION
Document Type: Research Article
Publication date: 01 December 2016
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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