Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications

Digital Watermarking (DW) becomes attractive for copyright protection, authentication, security, integrity verification to non-conventional application like Quality of Service (QoS) assessment of multimedia data in radio mobile communication. Several software have been developed on algorithms for watermarking purpose on digital data; however, hardware implementations are much more reliable and real-time systems can be designed through hardware implementation. In this work, a low-power, high-speed VLSI architecture for digital image watermarking algorithm in Discrete Fast Walsh-Hadamard Transform (DFWHT) domain is proposed. Data embedding process is assumed to be invisible, blind and is designed for both grayscale and binary watermarks. The watermarking algorithm is tested on software followed by its hardware implementation is developed. The architecture is realized using various Xilinx based Field Programmable Gate Array (FPGA) and programmable System-on-Chip (SoC) devices. From all the hardware implementations, Spartan-6 with device (xc6slx75-3fgg676) is selected, which operates at maximum operating frequency of 107 MHz, power 87 mW, latency 54.05 μs, throughput 15 Mbps and clock frequency of 50 MHz, to maintain a trade-off in power and delay meant for the required application.