An Effective Combinatorial Algorithm for Gate-Level Threshold Voltage Assignment
Author: Ghiasi, Soheil
Source: Journal of Low Power Electronics, Volume 2, Number 3, December 2006 , pp. 365-377(13)
Publisher: American Scientific Publishers
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Abstract:
We study the problem of sub-threshold leakage current optimization using dual threshold voltages under timing constraints. We present time budgeting as a methodology to perform implementation selection through which, we assign design components to specific threshold voltages to maximize leakage savings. We discuss several well-known formulations of time budgeting, and present a theoretical approach that can optimally and in polynomial time solve those problems under consecutive integer delay choices. This technique is further extended to perform very efficient implementation selection from a library of components with arbitrary integer delay choices. Experimental results show that our algorithm reduces the leakage current by close to an order of magnitude, with no or negligible delay penalty. Our algorithm outperforms the leakage savings of a recent LP-based competitor by 33%. More importantly, our results approach the theoretical limits of leakage savings using dual and multiple threshold voltages that are derived using Mixed Integer Linear Programming (MILP) formulation of the problem. On average, our results are only 0.74% worse than the optimal solutions, while our algorithm runs about 73 times faster than GNU MILP solver.Keywords: ALGORITHM; LOGIC SYNTHESIS; LEAKAGE; DELAY BUDGETING; IMPLEMENTATION SELECTION; SLACK DISTRIBUTION; THRESHOLD VOLTAGE ASSIGNMENT
Document Type: Research article
DOI: 10.1166/jolpe.2006.095
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