Surface Potential Based Analytical Modeling of Double Gate MOSFET with Si and Au Nano-Dots Embedded Gate Dielectric for Non-Volatile Memory Applications

In this paper we present an analytical study of Double Gate (DG) MOSFET memory devices with Si and Au nanocrystal embedded gate dielectric stacks. We considered an undoped long channel DG MOSFET, having a multilayer SiO₂ (5 nm)–Si/Au nc embedded Si₃N₄ (6 nm)–SiO₂ (7 nm) gate dielectric. From a quasi-1-D analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter following a trap-like model using the WKB approximation, we have investigated the Fowler Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. We evaluated the write-erase characteristics, gate tunneling currents, threshold voltage shifts and the output characteristics of the NVM devices from our analytical model. The performance of the nanoparticle embedded DGMOS memory device was compared with that of a DG SONOS NVM of similar dimensions. From the studies, the nc embedded devices showed better performance than the conventional SONOS DGMOS NVM. Among the two ncs compared the nc-Au embedded device emerged as the better performer in terms of higher charge density, faster charging, higher threshold voltage shift and better charge retention.