EURASIP Journal on Applied Signal Processing 
Volume 2003 (2003), Issue 6, Pages 530-542
doi:10.1155/S1110865703212105

An FPGA Implementation of (3,6)-Regular Low-Density Parity-Check Code Decoder

Tong Zhang1 and Keshab K. Parhi2

 1Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy 12180, NY, USA
2Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis 55455, MN, USA
Received 28 February 2002; Revised 6 December 2002

Abstract

Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed (3,k)-regular LDPC code partly parallel decoder architecture based on which we implement a 9216-bit, rate-1/2(3,6)-regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10−6 at 2 dB over AWGN channel while performing maximum 18 decoding iterations.