Abstract
To enable floating-point (FP) signal processing
applications in low-power mobile devices, we propose lightweight
floating-point arithmetic. It offers a wider range of
precision/power/speed/area trade-offs, but is wrapped in forms
that hide the complexity of the underlying implementations from
both multimedia software designers and hardware designers.
Libraries implemented in C++ and Verilog provide flexible and
robust floating-point units with variable bit-width formats,
multiple rounding modes and other features. This solution
bridges the design gap between software and hardware, and
accelerates the design cycle from algorithm to chip by avoiding
the translation to fixed-point arithmetic. We demonstrate the
effectiveness of the proposed scheme using the inverse discrete
cosine transform (IDCT), in the context of video coding, as an
example. Further, we implement lightweight floating-point IDCT
into hardware and demonstrate the power and area reduction.