Abstract
Field-programmable gate arrays (FPGAs) are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology
for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing
commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR) tools
by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool
Environment (LITE) is presented, which was developed to support the experimentation of power models and power optimization algorithms.
The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits
mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design,
and power is reduced by up to 19.4%, with an average power savings of 10.2%.