EURASIP Journal on Embedded Systems
Volume 2006 (2006), Article ID 16035, 12 pages
doi:10.1155/ES/2006/16035
Abstract
The use of field-programmable gate arrays (FPGAs) for digital
signal processing (DSP) has increased with the introduction of
dedicated multipliers, which allow the implementation of complex
algorithms. This architecture is especially effective for
data-intensive applications with extremes in data throughput. Recent
studies prove that the FPGAs offer better solutions for real-time
multiresolution video processing than any available processor, DSP
or general-purpose. FPGA design of critically sampled discrete
wavelet transforms has been thoroughly studied in literature over
recent years. Much less research was done towards FPGA design of
overcomplete wavelet transforms and advanced
wavelet-domain video processing algorithms. This paper
describes the parallel implementation of an advanced
wavelet-domain noise filtering algorithm, which uses a
nondecimated wavelet transform and spatially adaptive Bayesian
wavelet shrinkage. The implemented arithmetic is decentralized and
distributed over two FPGAs. The standard composite television video
stream is digitalized and used as a source for real-time video
sequences. The results demonstrate the effectiveness of the
developed scheme for real-time video processing.