EURASIP Journal on Applied Signal Processing 
Volume 2006 (2006), Article ID 15640, 9 pages
doi:10.1155/ASP/2006/15640

FPGA Prototyping of RNN Decoder for Convolutional Codes

Zoran Salcic, Stevan Berber, and Paul Secker

 Department of Electrical and Electronic Engineering, the University of Auckland, 38 Princess Street, Auckland 1020, New Zealand
Received 30 May 2005; Revised 29 November 2005; Accepted 21 January 2006

Recommended by Roger Woods

Abstract

This paper presents prototyping of a recurrent type neural network (RNN) convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that an RNN decoder for hard-decision decoding coupled with a simple hard-limiting neuron activation function results in a very low complexity, which easily fits into standard Altera FPGA. Moreover, the design methodology allowed modeling of complete testbed for prototyping RNN decoders in simulation and real-time environment (same FPGA), thus enabling evaluation of BER performance characteristics of the decoder for various conditions of communication channel in real time.