Abstract
A CMOS compatible method to fabricate non-planar silicon nanowires is realized on bulk silicon substrate using self-limiting oxidation with high control-capability of the nanowire size and shape. A predictive model of 2-D self-limiting oxidation for non-planar silicon nanodevices is also proposed and shows its good agreement with the experimental data in a wide range of oxidation temperatures, process time, and variety initial silicon core sizes. The shape evolution of silicon core during oxidation is successfully modeled and is verified by high-resolution SEM. Unlike traditional planar oxidation model which is limited in planar oxidation without any stress, the proposed predictive model is based on cylindrical Deal-Grove (D-G) equation including stress effect, and takes into account of the orientation dependence and the flow of SiO2 as viscous fluid, which can be successfully applied to process engineering of non-planar Si nanowire transistors.