Abstract
As contact resistance becomes a bottle-neck in scaled CMOS devices, there is a need for source/drain epitaxy with maximum dopant concentrations and optimized contacting schemes. In this paper we discuss the use of highly doped Si:P layers for the Source/Drain formation in Si bulk FinFETs. We report on the macroscopic and microscopic properties of the Si:P layers and discuss the details of the microstructure and the manifestation of Phosphorus-Vacancy complexes at high Phosphorus concentrations. We analyze how a post-epi thermal budget like spike or laser annealing modifies the microstructure and leads to an enhanced P activation and diffusion. We also zoom in on some of the integration aspects of the Si:P layers and discuss the benefit of the high-P concentration for the contact resistivity and the final device performance.