Tsung-Hao Chen
ABSTRACT
We develop a robust, efficient, and accurate tool, which integrates inductance extraction and simulation, called INDUCTWISE. This paper advances the state-of-the-art inductance extraction and simulation techniques and contains two major parts. In the first part, INDUCTWISE extractor, we discover the recently proposed inductance matrix sparsification algorithm, the K-method[1], albeit its great benefits of efficiency, has a major flaw on the stability. We provide both a counter example and a remedy for it. A window section algorithm is also presented to preserve the accuracy of the sparsification method. The second part, INDUCTWISE simulator, demonstrates great efficiency of integrating the nodal analysis formulation with the improved K-method. Experimental results show that INDUCTWISE has over 250x speedup compared to SPICE3. The proposed sparsification algorithm accelerates the simulator another 175x and speeds up the extractor 23.4x within 0.1% of error. INDUCTWISE can extract and simulate an 118K-conductor RKC circuit within 18 minutes. It has been well tested and released on the web for public usage. (http://vlsi.ece.wisc.edu/Inductwise.htm)
- H. Ji, A. Devgan, and W. Dai. Ksim: A stable and efficient rkc simulator for capturing on-chip inductance effect. In ASPDAC, June 2001. Google Scholar
Digital Library
- M.W. Beattie and L.T. Pileggi. Inductance 101: Modeling and extraction. In DAC, June 2001. Google ScholarDigital Library
- K. Gala, D. Blaauw, J. Wang, V. Zolotov, and M. Zhao. Inductance 101: Analysis and design issues. In DAC, June 2001. Google ScholarDigital Library
- A.E. Ruehli. Inductance calculatioin in a complex integrated curcuit environment. IBM Journal of Research and Development, pages 470--481, September 1972.Google ScholarDigital Library
- M. Kamon, M.J. Tsuk, and J.K. White. Fasthenry: A multipole-accelerated 3-d inductance extraction program. In DAC, June 1993. Google ScholarDigital Library
- N. Chang, S. Lin, J. Lillis, and C.K. Cheng. Inteconnect Analysis and Synthesis. John Wiley & Sons Inc., 2000. Google ScholarDigital Library
- Z. He, M. Celik, and L.T. Pileggi. Spie: Sparse partial inductance extraction. In DAC, 1997. Google ScholarDigital Library
- B. Krauter and L.T. Pileggi. Generating sparse partial inductance matrices with guaranteed stability. In ICCAD, November 1995. Google ScholarDigital Library
- K.L. Shepard and Z. Tian. Return-limited inductances: A practical approach to on-chip inductance extraction. IEEE Trans. on Computer Aided Design of Integrated Ciurcuits and Systems, 19(4):425--436, April 2000. Google ScholarDigital Library
- K. Gala, V. Zolotov, R. Panda, B. Young, J. Wang, and D. Blaauw. On-chip inductance modeling and analysis. In DAC, June 2000. Google ScholarDigital Library
- M.W. Beattie and L.T. Pileggi. Modeling magnetic coupling for on-chip interconnect. In DAC, June 2001. Google ScholarDigital Library
- A. Devgan, H. Ji, and W. Dai. How to efficiently capture on-chip inductance effects: Introducing a new circuit element k. In ICCAD, November 2000. Google ScholarDigital Library
- http://whatis.techtarget.com/definition/0,sid9_gci531197,00.html.Google Scholar
- H. Zheng, B. Krauter, M. Beattie, and L. Pileggi. Window-based susceptance models for large-scale rlc circuit analysis. In DATE, 2002. Google ScholarDigital Library
- T.H. Chen and C.C.P. Chen. Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods. In DAC, June 2001. Google ScholarDigital Library
- L.W. Nagel. Spice2: A computer program to simulate semiconductor circuits. U.C. Berkely, ERL Memo ERL-M520, 1975.Google Scholar
Index Terms
- INDUCTWISE: inductance-wise interconnect simulator and extractor
Recommendations
INDUCTWISE: inductance-wise interconnect simulator and extractor
A robust, efficient, and accurate inductance extraction and simulation tool, INDUCTWISE, is developed and described in this paper. This work advances the state-of-the-art inductance extraction and simulation techniques, and has several major ...
Analysis of power-performance for ultra-thin-body GeOI logic circuits
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and designThis work analyzes the power-performance of the emerging Ultra-Thin-Body (UTB) GeOI devices for logic circuit applications. The impacts of temperature and Vdd scaling on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI ...
Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs
Aggressive technology scaling as per Moore's law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, ...
Comments