J. L. Heath
- Jan L. Heath, "A Study of Reduced Instruction Set Computers", M.S. Thesis, EEE Dept., North Dakota State University, 1983Google Scholar
- R. Grappel, and J. Hemenway, "A tale of four uPs: Benchmarks quantify performance," Electronic Desian News. Vol. 26, No. 7, April I, 1981, pp. 179--265.Google Scholar
- D. Patterson, and C. Sequin, "A VLSI RISC," IEEE Comuter. Vol. 15, No. 9, September, 1982, pp. 8--18.Google ScholarDigital Library
- R. Piepho, "Comparative Evaluation of the RISC I Architecture Via the Computer Family Architecture Benchmarks," Research Project, University of California, Berkeley, August 17, 1981.Google Scholar
- D. Patterson, and D. Ditzel, "The Case for the Reduced Instruction Set Computer," Computer Architecture News. Vol. 8, No. 6, October, 1980, pp. 25--33. Google ScholarDigital Library
- D. Fitzpatrick, D. Patterson, C. Sequin, et al., "A RISCy Approach to VLSI," Computer Architecture News. Vol. 10, No. 1, March 1982, pp. 28--32. Google ScholarDigital Library
- R. Colwell, C. Hitchcock III, E. Jensen, "Peering Through the RISC/CISC Fog: An Outline of Research," Cormputer Architecture News. Vol. 11, No. 1, March 1983, pp. 44--50. Google ScholarDigital Library
Index Terms
- Re-evaluation of the RISC I
Index terms have been assigned to the content through auto-classification.
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