ABSTRACT
Hybrid dataflow/von Neumann processors expose their processing units and datapaths to the compiler to exploit the instruction-level parallelism of sequential programs. Generating code from dataflow graphs for such processors that use FIFO-buffered datapaths requires (1) an allocation that maps the nodes of the dataflow graph to the processing units (PUs) of the processor, and (2) a schedule for firing the nodes on the PUs that does not violate the FIFO behavior of the buffers. In previous work, we have encoded the constraints required to ensure the FIFO behavior for the code generation as a SAT problem. In this paper, we consider PU allocation and node scheduling in isolation, inspired by the traditional compilers, which also treat register allocation and instruction scheduling as separate problems. If a schedule is given, we reduce the PU allocation problem to a graph coloring problem so that heuristics can solve it efficiently. We also perform interference analysis, similar to register interference analysis to reveal special properties of the PU allocation graph. If a PU allocation is given, the scheduling problem is almost reduced to a 2SAT problem so that it can also be solved efficiently.
- W. Ackerman. 1982. Data Flow Languages. IEEE Computer 15, 2 (February 1982), 15--25.Google ScholarDigital Library
- T. Agerwala and K.P. Arvind. 1982. Data Flow Systems. IEEE Computer 15, 2 (February 1982), 10--13.Google ScholarDigital Library
- S.R. Anapalli, K.C. Chakilam, and T.W. O'Neil. 2009. Static Scheduling for Cyclo-static Data Flow Graphs. In Parallel and Distributed Processing Techniques and Applications (PDPTA), H.R. Arabnia (Ed.). CSREA Press, Las Vegas, Nevada, USA, 302--306.Google Scholar
- M. Anders, A. Bhagyanath, and K. Schneider. 2018. On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units. In Application of Concurrency to System Design (ACSD), T. Chatain and R. Grosu (Eds.). IEEE Computer Society, Bratislava, Slovakia, 115--124.Google Scholar
- Arvind, D.E. Culler, and K. Ekanadham. 1988. The Price of Asynchronous Parallelism: An Analysis of Dataflow Architectures. In Proceedings of the conference on CONPAR 88. British Computer Society, Manchester, England, UK, 541--555.Google Scholar
- Arvind, D.E. Culler, and G.K. Maa. 1988. Assessing the Benefits of Fine-Grain Parallelism in Dataflow Programs. International Journal of Supercomuter Applications 2, 3 (1988), 10--36.Google ScholarDigital Library
- J. Backus. 1978. Can Programming be Liberated from the von Neumann Style? Communications of the ACM (CACM) 21, 8 (August 1978), 613--641.Google ScholarDigital Library
- S.S. Battacharyya, P.K. Murthy, and E.A. Lee. 1996. Software Synthesis from Dataflow Graphs. Kluwer Adacemic Publishers.Google Scholar
- A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone. 2003. The Synchronous Languages Twelve Years Later. Proc. IEEE 91, 1 (2003), 64--83.Google ScholarCross Ref
- A. Benveniste, P. Le Guernic, and C. Jacquemot. 1991. Synchronous programming with events and relations: the SIGNAL language and its semantics. Science of Computer Programming 16, 2 (September 1991), 103--149.Google ScholarDigital Library
- A. Bhagyanath. 2020. Code Generation for Synchronous Control Asynchronous Dataflow Architectures. Ph. D. Dissertation. Department of Computer Science, University of Kaiserslautern, Germany. PhD.Google Scholar
- A. Bhagyanath and K. Schneider. 2016. Optimal Compilation for Exposed Datapath Architectures with Buffered Processing Units by SAT Solvers. In Formal Methods and Models for Codesign (MEMOCODE), E. Leonard and K. Schneider (Eds.). IEEE Computer Society, Kanpur, India, 143--152.Google Scholar
- A. Bhagyanath and K. Schneider. 2017. Exploring different execution paradigms in exposed datapath architectures with buffered processing units. In International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Y.N. Patt and S.K. Nandy (Eds.). IEEE Computer Society, Pythagorion, Greece, 1--10.Google Scholar
- A. Bhagyanath and K. Schneider. 2017. Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units. In Application of Concurrency to System Design (ACSD), A. Legay and K. Schneider (Eds.). IEEE Computer Society, Zaragoza, Spain, 106--115.Google Scholar
- A. Bhagyanath and K. Schneider. 2022. Buffer Allocation for Exposed Datapath Architectures. In International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE Computer Society, Penang, Malaysia, 18--25.Google Scholar
- A. Bhagyanath and K. Schneider. 2023. Program Balancing in Compilation for Buffered Hybrid Dataflow Processors. In Computer Architectures and Platforms (CAP) at Computer Software and Applications Conference (COMPSAC). IEEE Computer Society, Torino, Italy.Google Scholar
- S.S. Bhattacharyya, E.F. Deprettere, and B.D. Theelen. 2013. Dynamic Dataflow Graphs. In Handbook of Signal Processing Systems. Springer, 905--944.Google Scholar
- G. Bilsen, M. Engels, R. Lauwereins, and J. Peperstraete. 1996. Cyclo-static dataflow. IEEE Transactions on Signal Processing 44, 2 (February 1996), 397--408.Google ScholarDigital Library
- G. Blake, R.G. Dreslinski, and T. Mudge. 2009. A Survey of Multicore Processors. IEEE Signal Processing Magazine 26, 6 (November 2009), 26--37.Google ScholarCross Ref
- F.J. Brandenburg. 1988. On the Intersection of Stacks and Queues. Theoretical Computer Science 58 (1988), 69--80.Google ScholarDigital Library
- J.T. Buck. 1993. Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model. Ph.D. Dissertation. University of California, Berkeley, California, USA. PhD.Google Scholar
- J.T. Buck. 1994. Static Scheduling and Code Generation from Dynamic Dataflow Graphs With Integer-Valued Control Streams. In Asilomar Conference on Signals, Systems, and Computers. IEEE Computer Society, Pacific Grove, CA, USA, 508--513.Google ScholarCross Ref
- J. Buck and E.A. Lee. 1995. The Token Flow Model. In Advanced Topics in Dataflow Computing and Multithreading, L. Bic, G.R. Gao, and J.-L. Gaudiot (Eds.). IEEE Computer Society, Hamilton Island, Queensland, Australia, 267--290.Google Scholar
- R. Buehrer and K. Ekanadham. 1987. Incorporating Dataflow Ideas into von Neumann Processors for Parallel Execution. IEEE Transactions on Computers (T-C) 36, 12 (December 1987), 1515--1522.Google Scholar
- D. Burger, S.W. Keckler, K.S. McKinley, M. Dahlin, L.K. John, C. Lin, C.R. Moore, J. Burrill, R.G. McDonald, and W. Yoder. 2004. Scaling to the End of Silicon with EDGE Architectures. IEEE Computer 37, 7 (July 2004), 44--55.Google ScholarDigital Library
- P. Caspi, N. Halbwachs, D. Pilaud, and J.A. Plaice. 1987. LUSTRE: A declarative language for programming synchronous systems. In Principles of Programming Languages (POPL). ACM, Munich, Germany, 178--188.Google Scholar
- G. Chaitin. 2004. Register allocation and spilling via graph coloring. ACM SIGPLAN Notices 39, 4 (April 2004), 66--74.Google ScholarDigital Library
- G.J. Chaitin, M.A. Auslander, A.K. Chandra, J. Cocke, M.E. Hopkins, and P.W. Markstein. 1981. Register Allocation via Graph Coloring. Computer Languages 6, 2 (1981), 47--57.Google ScholarDigital Library
- A. Cherubini, C. Citrini, S. Crespi Reghizzi, and D. Mandrioli. 1991. QRT FIFO automata, breadth-first grammars and their relations. Theoretical Computer Science 85 (1991), 171--203.Google ScholarDigital Library
- G. Cichon, P. Robelly, H. Seidel, E. Matúš, M. Bronzel, and G. Fettweis. 2004. Synchronous Transfer Architecture (STA). In International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation. Springer Berlin Heidelberg, Samos, Greece, 343--352.Google Scholar
- H. Corporaal. 1994. Design of Transport Triggered Architectures. In Great Lakes Symposium on VLSI (GLSVLSI). IEEE Computer Society, Notre Dame, IN, USA, 130--135.Google Scholar
- H. Corporaal. 1999. TTAs: Missing the ILP complexity wall. Journal of Systems Architecture 45, 12--13 (June 1999), 949--973.Google Scholar
- H. Corporaal, J. Janssen, and M. Arnold. 2000. Computation in the Context of Transport Triggered Architectures. International Journal of Parallel Programming 28, 4 (August 2000), 401--427.Google Scholar
- R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck. 1991. Efficiently computing static single assignment form and the control dependence graph. ACM Transactions on Programming Languages and Systems (TOPLAS) 13, 4 (October 1991), 451--490.Google ScholarDigital Library
- M. Dahlem, A. Bhagyanath, and K. Schneider. 2018. Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP. Theory and Practice of Logic Programming (TPLP) 18, 1 (January 2018), 438--451.Google Scholar
- A.L. Davis. 1978. The architecture and system method of DDM1: A recursively structured Data Driven Machine. In International Symposium on Computer Architecture (ISCA). ACM, Palo Alto, CA, USA, 210--215.Google ScholarDigital Library
- J.B. Dennis. 1974. First Version of a Data-Flow Procedure Language. In Programming Symposium (LNCS, Vol. 19), B. Robinet (Ed.). Springer, Paris, France, 362--376.Google ScholarCross Ref
- J.B. Dennis. 1980. Data Flow Supercomputers. IEEE Computer 13, 11 (November 1980), 48--56.Google ScholarDigital Library
- J.B. Dennis and D.P. Misunas. 1975. A Preliminary Architecture for a Basic Dataflow Processor. In International Symposium on Computer Architecture (ISCA), W.K. King and O. Garcia (Eds.). ACM, Houston, TX, USA, 126--132.Google Scholar
- G. A. Dirac. 1961. On rigid circuit graphs. Abhandlungen aus dem Mathematischen Seminar der Universität Hamburg 25 (April 1961), 71--76.Google Scholar
- V. Dujmović‡, D. Eppstein, R. Hickingbotham, P. Morin, and D.R. Wood. 2022. Stack-Number is Not Bounded by Queue-Number. Combinatorica 42, 2 (2022), 151--164.Google ScholarDigital Library
- M. Engels, G. Bilsen, R. Lauwereins, and J. Peperstraete. 1994. Cyclo-static dataflow: Model and implementation. In Asilomar Conference on Signals, Systems and Computers (ACSSC). IEEE Computer Society, Pacific Grove, California, USA.Google Scholar
- M. Engels, G. Bilsen, R. Lauwereins, and J. Peperstraete. 1995. Cyclo-static dataflow. In International Conference on Acoustics, Speech and Signal Processing (ICASSP). IEEE Computer Society, Detroit, Michigan, USA, 3255--3258.Google Scholar
- D.D. Gajski, D.A. Padua, D.J. Kuck, and R.H. Kuhn. 1982. A Second Opinion of Data Flow Machines and Languages. IEEE Computer 15, 2 (February 1982), 58--69.Google ScholarDigital Library
- S. Gatzka and C. Hochberger. 2005. The AMIDAR Class of Reconfigurable Processors. The Journal of Supercomputing 32, 2 (2005), 163--181.Google ScholarDigital Library
- T. Gautier, P. Le Guernic, and L. Besnard. 1987. SIGNAL, a declarative language for synchronous programming of real-time systems. In Functional Programming Languages and Computer Architecture (LNCS, Vol. 274), G. Kahn (Ed.). Springer, Portland, Oregon, USA, 257--277.Google Scholar
- F. Gavril. 1972. Algorithms for Minimum Coloring, Maximum Clique, Minimum Covering by Cliques, and Maximum Independent Set of a Chordal Graph. SIAM J. Comput. 1 (June 1972), 180--187.Google Scholar
- V. Govindaraju, C.-H. Ho, T. Nowatzki, J. Chhugani, N. Satish, K. Sankaralingam, and C. Kim. 2012. DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing. IEEE Micro 33, 5 (2012), 38--51.Google ScholarDigital Library
- V. Govindaraju, C.-H. Ho, and K. Sankaralingam. 2011. Dynamically Specialized Datapaths for Energy Efficient Computing. In International Symposium on High Performance Computer Architecture. IEEE Computer Society, San Antonio, TX, USA, 503--514.Google Scholar
- V.G. Grafe, G.S. Davidson, J.E. Hoch, and V.P. Holmes. 1989. The Epsilon dataflow processor. ACM SIGARCH Computer Architecture News 17, 3 (June 1989), 36--45.Google ScholarDigital Library
- J.R. Gurd, C.C. Kirkham, and I. Watson. 1985. The Manchester prototype dataflow computer. Commun. ACM 28, 1 (January 1985), 34--52.Google ScholarDigital Library
- G. Hajos. 1957. Über eine Art von Graphen. Internationale Mathematische Nachrichten 11 (April 1957), 65.Google Scholar
- N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud. 1991. The Synchronous Dataflow Programming Language LUSTRE. Proc. IEEE 79, 9 (September 1991), 1305--1320.Google ScholarCross Ref
- Y. He, D. She, B. Mesman, and H. Corporaal. 2011. MOVE-Pro: A low power and high code density TTA architecture. In International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation. IEEE, Samos, Greece, 294--301.Google Scholar
- L.S. Heath, F.T Leighton, and A.L. Rosenberg. 1992. Comparing Queues and Stacks as Mechanisms for Laying out Graphs. SIAM Journal on Discrete Mathematics 5, 3 (August 1992), 398--412.Google ScholarDigital Library
- L.S. Heath and S.V. Pemmaraju. 1996. Recognizing Leveled-Planar DAGs in Linear Time. In Graph Drawing (GD) (LNCS, Vol. 1027), F.J. Brandenburg (Ed.). Springer, Passau, Germany, 300--311.Google Scholar
- L.S. Heath and S.V. Pemmaraju. 1997. Stack and Queue Layouts of Posets. SIAM J. Comput. 10, 4 (1997), 599--625.Google ScholarDigital Library
- L.S. Heath and S.V. Pemmaraju. 1999. Stack and Queue Layouts of Directed Acyclic Graphs: Part II. SIAM J. Comput. 28, 5 (1999), 1588--1626.Google ScholarDigital Library
- L.S. Heath, S.V. Pemmaraju, and A.N. Trenk. 1999. Stack and Queue Layouts of Directed Acyclic Graphs: Part I. SIAM J. Comput. 28, 4 (1999), 1510--1539.Google ScholarDigital Library
- L.S. Heath and A.L. Rosenberg. 1992. Comparing Queues and Stacks As Machines for Laying Out Graphs. SIAM J. Comput. 21, 5 (October 1992), 927--958.Google ScholarDigital Library
- Y. Herath, Y. Yamaguchi, N. Saito, and T. Yuba. 1988. Dataflow Computing Models, Languages, and Machines for Intelligence Computations. IEEE Transactions on Software Engineering 14, 12 (December 1988), 1805--1828.Google ScholarDigital Library
- J. Hoogerbrugge and H. Corporaal. 1994. Transport-Triggering vs. Operation-Triggering. In Compiler Construction (CC) (LNCS, Vol. 786), P. Fritzson (Ed.). Springer, Edinburgh, UK, 435--449.Google Scholar
- R.A. Iannucci. 1988. Towards a Dataflow/von Neumann Hybrid Architecture. In International Symposium on Computer Architecture (ISCA), H. Siegel (Ed.). IEEE Computer Society, Honolulu, Hawaii, USA, 131--140.Google ScholarCross Ref
- W.M. Johnston, J.R.P. Hanna, and R.J. Millar. 2004. Advances in Dataflow Programming Languages. ACM Computing Surveys (CSUR) 36, 1 (March 2004), 1--34.Google ScholarDigital Library
- P. Jääskeläinen, H. Kultala, T. Viitanen, and J. Takala. 2015. Code Density and Energy Efficiency of Exposed Datapath Architectures. Journal of Signal Processing Systems 80, 1 (July 2015), 49--64.Google ScholarDigital Library
- P. Jääskeläinen, A. Tervo, G.P. Vayá, T. Viitanen, N. Behmann, and H. Blume. 2018. Transport-Triggered Soft Cores. In International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE Computer Society, Vancouver, BC, Canada, 83--90.Google Scholar
- M. Jünger, S. Leipert, and P. Mutzel. 1998. Level Planarity Testing in Linear Time. In Graph Drawing (GD) (LNCS, Vol. 1547), S.H. Whitesides (Ed.). Springer, Montréal, Canada, 224--237.Google Scholar
- G. Kahn. 1974. The Semantics of a Simple Language for Parallel Programming. In Information Processing, J.L. Rosenfeld (Ed.). North-Holland, Stockholm, Sweden, 471--475.Google Scholar
- G. Kahn and D.B. MacQueen. 1977. Coroutines and networks of parallel processes. In Information Processing, B. Gilchrist (Ed.). North-Holland, Toronto, Canada, 993--998.Google Scholar
- R.M. Karp. 1972. Reducibility among Combinatorial Problems. In Complexity of Computer Computations, R.E. Miller and J.W. Thatcher (Eds.). Plenum Press, New York, Yorktown Heights, New York, USA, 85--103.Google Scholar
- R.M. Karp and R.E. Miller. 1966. Properties of a Model for Parallel Computations: Determinacy, Termination, Queueing. SIAM Journal on Applied Mathematics (SIAP) 14, 6 (November 1966), 1390--1411.Google ScholarDigital Library
- P. Le Guernic, T. Gauthier, M. Le Borgne, and C. Le Maire. 1991. Programming real-time applications with SIGNAL. Proc. IEEE 79, 9 (1991), 1321--1336.Google ScholarCross Ref
- E.A. Lee. 1991. Consistency in Dataflow Graphs. IEEE Transactions on Parallel and Distributed Systems (TPDS) 2, 2 (1991), 223--235.Google ScholarDigital Library
- E.A. Lee and D.G. Messerschmitt. 1987. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing. IEEE Transactions on Computers (T-C) 36, 1 (January 1987), 24--35.Google Scholar
- E.A. Lee and D.G. Messerschmitt. 1987. Synchronous Data Flow. Proc. IEEE 75, 9 (September 1987), 1235--1245.Google ScholarCross Ref
- E.A. Lee and T. Parks. 1995. Dataflow Process Networks. Proc. IEEE 83, 5 (May 1995), 773--801.Google ScholarCross Ref
- C.G. Lekkerkerker and J.C. Boland. 1962. Representation of a finite graph by a set of intervals on the real line. Fundamenta Mathematicae 51 (1962), 45--64.Google ScholarCross Ref
- V. Milutinovic, M. Kotlar, M. Stojanovic, I. Dundic, N. Trifunovic, and Z. Babovic. 2017. Dataflow Supercomputing Essentials - Algorithms, Applications and Implementations. Springer.Google Scholar
- V. Milutinovic, J. Salom, N. Trifunovic, and R. Giorgi. 2015. Guide to Dataflow Supercomputing - Basic Concepts, Case Studies, and a Detailed Example. Springer.Google Scholar
- M. Mishra, T.J. Callahan, T. Chelcea, G. Venkataramani, M. Budiu, and S.C. Goldstein. 2006. Tartan: evaluating spatial computation for whole program execution. In Architectural Support for Programming Languages and Operating Systems (ASPLOS), J.P. Shen and M.R. Martonosi (Eds.). ACM, San Jose, California, USA, 163--174.Google Scholar
- R.S. Nikhil. 1989. Can Dataflow Subsume Von Neumann Computing?. In International Symposium on Computer Architecture (ISCA). IEEE Computer Society, Jerusalem, Israel, 262--272.Google Scholar
- G. Papadopoulos and D. Culler. 1990. Monsoon: An Explicit Token-Store Architecture. In International Symposium on Computer Architecture (ISCA), J.-L. Baer and L. Snyder (Eds.). IEEE Computer Society, Seattle, Washington, USA, 82--91.Google Scholar
- S.V. Pemmaraju. 1992. Exploring the powers of stacks and queues via graph layouts. Ph. D. Dissertation. Virigina Polytechnic Institute and State University, Blacksburg, VA, USA. PhD.Google Scholar
- J. Roob, A. Bhagyanath, and K. Schneider. 2023. Towards Buffers as a Scalable Alternative to Registers for Processor-Local Memory. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (ITG-Fachbericht). VDE, Freiburg, Germany, 1--12.Google Scholar
- J. Rumbaugh. 1977. A Data Flow Multiprocessor. IEEE Transactions on Computers (T-C) 26, 2 (February 1977), 138--146.Google Scholar
- K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, N. Ranganathan, D. Burger, S.W. Keckler, R.G. Mcdonald, and C.R. Moore. 2004. TRIPS: A Polymorphous Architecture for Exploiting ILP, TLP, and DLP. ACM Transactions on Architecture and Code Optimization (TACO) 1, 1 (2004), 62--93.Google ScholarDigital Library
- K. Schneider. 2021. Translating Structured Sequential Programs to Dataflow Graphs. In Formal Methods and Models for Codesign (MEMOCODE), I. Saha and L. Zhang (Eds.). ACM, Beijing, China, 66--77.Google Scholar
- K. Schneider and A. Bhagyanath. 2023. Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann Architectures. Transactions on Embedded Computing Systems (TECS) (2023), 1--25.Google Scholar
- K. Schneider, A. Bhagyanath, and J. Roob. 2022. Code Generation Criteria for Buffered Exposed Datapath Architectures from Dataflow Graphs. In Languages, Compilers, and Tools for Embedded Systems (LCTES), K. Lee (Ed.). ACM, San Diego, California, United States, 133--145.Google Scholar
- J.A. Sharp (Ed.). 1992. Data Flow Computing - Theory and Practice. Ablex Publishing.Google Scholar
- S. Swanson. 2006. The WaveScalar Architecture. Ph.D. Dissertation. University of Washington. PhD.Google Scholar
- S. Swanson, K. Michelson, A. Schwerin, and M. Oskin. 2003. WaveScalar. In Microarchitecture (MICRO). IEEE Computer Society, San Diego, California, USA, 291--302.Google Scholar
- S. Swanson, A. Schwerin, M. Mercaldi, A. Petersen, A. Putnam, K. Michelson, M. Oskin, and S.J. Eggers. 2007. The WaveScalar Architecture. ACM Transactions on Computer Systems (TOCS) 25, 2 (May 2007), 1--54.Google ScholarDigital Library
- M.B. Taylor. 1999. Design Decisions in the Implementation of a RAW Architecture Workstation. Master's thesis. Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, USA. Master.Google Scholar
- M.B. Taylor, J.S. Kim, J.E. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffmann, P. Johnson, J.W. Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M.I. Frank, S.P. Amarasinghe, and A. Agarwal. 2002. The RAW Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. IEEE Micro 22, 2 (March/April 2002), 25--35.Google ScholarDigital Library
- M. Thuresson, M. Själander, M. Björk, L. Svensson, P. Larsson-Edefors, and P. Stenstrom. 2008. FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. Journal of Signal Processing Systems 57, 1 (April 2008), 5--19.Google Scholar
- K.R. Traub, G.M. Papadopoulos, M.J. Beckerle, J.E. Hicks, and J. Young. 1991. Overview of the Monsoon Project. In International Conference on Computer Design (ICCD). IEEE Computer Society, Cambridge, Massachusetts, USA, 150--155.Google Scholar
- T. Ungerer. 1993. Datenflußrechner. Teubner.Google Scholar
- A.H. Veen. 1986. Dataflow Machine Architecture. ACM Computing Surveys (CSUR) 18, 4 (December 1986), 365--396.Google ScholarDigital Library
- G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson, and M.B. Taylor. 2010. Conservation cores: reducing the energy of mature computations. In Architectural Support for Programming Languages and Operating Systems (ASPLOS), J.C. Hoe and V.S. Adve (Eds.). ACM, Pittsburgh, Pennsylvania, USA, 205--218.Google Scholar
- R. Vollmar. 1970. Über einen Automaten mit Pufferspeicherung. Computing 5, 1 (1970), 57--70.Google ScholarCross Ref
- E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, J. Babb, S. Amarasinghe, and A. Agarwal. 1997. Baring it all to Software: RAW Machines. IEEE Computer 30, 9 (September 1997), 86--93.Google ScholarDigital Library
- I. Watson and J.R. Gurd. 1982. A Practical Data Flow Computer. IEEE Computer 15, 2 (January 1982), 51--57.Google ScholarDigital Library
- F. Yazdanpanah, C. Alvarez-Martinez, D. Jimenez-Gonzalez, and Y. Etsion. 2014. Hybrid Dataflow/von-Neumann Architectures. IEEE Transactions on Parallel and Distributed Systems 25, 6 (June 2014), 1489--1509.Google ScholarDigital Library
- T. Yuba, K. Hiraki, T. Shimada, S. Sekiguchi, and K. Nishida. 1987. The SIGMA-1 dataflow computer. In Fall Joint Computer Conference on Exploring technology: today and tomorrow (FJCC), S.A. Szygenda (Ed.). ACM, Chicago, IL, USA, 578--585.Google Scholar
Index Terms
- Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann Architectures
Recommendations
Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann Architectures
Dataflow process networks (DPNs) provide a convenient model of computation that is often used to model system behavior in model-based designs. With fixed sets of nodes, they are also used as dataflow graphs as an intermediate program representation by ...
Buffer minimization in earliest-deadline first scheduling of dataflow graphs
LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systemsSymbolic schedulability analysis of dataflow graphs is the process of synthesizing the timing parameters (i.e. periods, phases, and deadlines) of actors so that the task system is schedulable and achieves a high throughput when using a specific ...
Buffer minimization in earliest-deadline first scheduling of dataflow graphs
LCTES '13Symbolic schedulability analysis of dataflow graphs is the process of synthesizing the timing parameters (i.e. periods, phases, and deadlines) of actors so that the task system is schedulable and achieves a high throughput when using a specific ...
Comments