Jiayao Wu
Weisheng Zhao
ABSTRACT
Neural network (NN) is one of the most significant methods to accomplish complex targets, which is widely used in image recognition, natural language processing and so on. NN demands tremendous amount of parallel Multiply-and-accumulation (MAC) operations that would affect the speed and power efficiency. Thus, how to accelerate MAC and reduce the power consumption, especially for multiplication, is a critical concern. Perpendicular-anisotropy spin-orbit torque (SOT) magnetic random access memory (MRAM) with spin transfer torque (STT) assisted is leveraged in this work, which is perfect to be used for NN because of its non-volatility, power efficiency and ultrafast operation. In addition, Booth arithmetic is an excellent method to reduce the partial products of the multiplication for acceleration. In this work, an in-memory Booth multiplier based on MRAM is designed and analyzed through simulation. Compared with the in-SRAM counterpart, our design saved 70.4% energy of the decoding part, which shows great improvement.
- Oludare Isaac Abiodun, Aman Jantan, Abiodun Esther Omolara, Kemi Victoria Dada, Nachaat AbdElatif Mohamed, and Humaira Arshad. 2018. State-of-the-art in artificial neural network applications: A survey. Heliyon 4, 11 (2018), e00938.Google Scholar
Cross Ref
- Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David Blaauw, and Reetuparna Das. 2017. Compute caches. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 481--492.Google ScholarCross Ref
- Luc Berger. 1996. Emission of spin waves by a magnetic multilayer traversed by a current. Physical Review B 54, 13 (1996), 9353.Google ScholarCross Ref
- Yen-Jen Chang, Yu-Cheng Cheng, Shao-Chi Liao, and Chun-Huo Hsiao. 2020. A low power radix-4 booth multiplier with pre-encoded mechanism. Ieee Access 8 (2020), 114842--114853.Google ScholarCross Ref
- Costas Efstathiou, Zaher Owda, and Yiorgos Tsiatouhas. 2013. New high-speed multioutput carry look-ahead adders. IEEE Transactions on Circuits and Systems II: Express Briefs 60, 10 (2013), 667--671.Google ScholarCross Ref
- Yabin Fan, Xufeng Kou, Pramey Upadhyaya, Qiming Shao, Lei Pan, Murong Lang, Xi-aoyu Che, Jianshi Tang, Mohammad Montazeri, Koichi Murata, et al. 2016. Electric-field control of spin-orbit torque in a magnetically doped topological insulator. Nature nanotechnology 11, 4 (2016), 352--359.Google Scholar
- Daniele Ielmini and H-S Philip Wong. 2018. In-memory computing with resistive switching devices. Nature electronics 1, 6 (2018), 333--343.Google Scholar
- Shiann-Rong Kuang and Jiun-Ping Wang. 2009. Design of power-efficient configurable booth multiplier. IEEE Transactions on Circuits and Systems I: Regular Papers 57, 3 (2009), 568--580.Google ScholarDigital Library
- Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim, Hongjung Kim, Ju Young Kim, Young Jun Park, Jae Hwan Kim, Dae Suk Kim, Heat Bit Park, Jin Wook Shin, et al. 2014. 25.2 A 1.2 V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). IEEE, 432--433.Google ScholarCross Ref
- Ioan Mihai Miron, Kevin Garello, Gilles Gaudin, Pierre-Jean Zermatten, Marius V Costache, Stéphane Auffret, Sébastien Bandiera, Bernard Rodmacq, Alain Schuhl, and Pietro Gambardella. 2011. Perpendicular switching of a single ferromagnetic layer induced by in-plane current injection. Nature 476, 7359 (2011), 189--193.Google Scholar
- J Thomas Pawlowski. 2011. Hybrid memory cube (HMC). In 2011 IEEE Hot chips 23 symposium (HCS). IEEE, 1--24.Google Scholar
- Noriyuki Sato, Gary A Allen, William P Benson, Benjamin Buford, Atreyee Chakraborty, Michael Christenson, Tanay A Gosavi, Philip E Heil, Nafees A Kabir, Brian J Krist, et al. 2020. CMOS compatible process integration of SOT-MRAM with heavy-metal bi-layer bottom electrode and 10ns field-free SOT switching with STT assist. In 2020 IEEE Symposium on VLSI Technology. IEEE, 1--2.Google ScholarCross Ref
- Abu Sebastian, Manuel Le Gallo, Riduan Khaddam-Aljameh, and Evangelos Eleftheriou. 2020. Memory devices and applications for in-memory computing. Nature nanotechnology 15, 7 (2020), 529--544.Google Scholar
- John C Slonczewski. 1996. Current-driven excitation of magnetic multilayers. Journal of Magnetism and Magnetic Materials 159, 1--2 (1996), L1--L7.Google ScholarCross Ref
- Kelly Liew Suet Swee and Lo Hai Hiung. 2012. Performance comparison review of Radix-based multiplier designs. In 2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012), Vol. 2. IEEE, 854--859.Google Scholar
- C Vinoth, VS Kanchana Bhaaskaran, B Brindha, S Sakthikumaran, V Kavinilavu, B Bhaskar, M Kanagasabapathy, and B Sharath. 2011. A novel low power and high speed Wallace tree multiplier for RISC processor. In 2011 3rd International Conference on Electronics Computer Technology, Vol. 1. IEEE, 330--334.Google ScholarCross Ref
- Mengxing Wang, Wenlong Cai, Daoqian Zhu, Zhaohao Wang, Jimmy Kan, Zhengyang Zhao, Kaihua Cao, Zilu Wang, Youguang Zhang, Tianrui Zhang, et al. 2018. Field-free switching of a perpendicular magnetic tunnel junction through the interplay of spin-orbit and spin-transfer torques. Nature electronics 1, 11 (2018), 582--588.Google Scholar
- Zhaohao Wang, Haochang Zhou, Mengxing Wang, Wenlong Cai, Daoqian Zhu, Jacques-Olivier Klein, and Weisheng Zhao. 2019. Proposal of toggle spin torques magnetic RAM for ultrafast computing. IEEE Electron Device Letters 40, 5 (2019), 726--729.Google ScholarCross Ref
- Wei Xu, Hongbin Sun, Xiaobin Wang, Yiran Chen, and Tong Zhang. 2009. Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM). IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, 3 (2009), 483--493.Google ScholarDigital Library
- Zhi Yang, Kuiqing He, Zeqing Zhang, Yao Lu, Zheng Li, Yijiao Wang, Zhaohao Wang, and Weisheng Zhao. 2022. A Novel Computing-in-Memory Platform Based on Hybrid Spintronic/CMOS Memory. IEEE Transactions on Electron Devices 69, 4 (2022), 1698--1705.Google ScholarCross Ref
- Received 21 September 2022; accepted 14 November 2022Google Scholar
Index Terms
- An In-memory Booth Multiplier Based on Non-volatile Memory for Neural Network Applications
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