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Cross-layer fault-space pruning for hardware-assisted fault injection

Published:24 June 2018Publication History

ABSTRACT

With shrinking structure sizes, soft-error mitigation has become a major challenge in the design and certification of safety-critical embedded systems. Their robustness is quantified by extensive fault-injection campaigns, which on hardware level can nevertheless cover only a tiny part of the fault space.

We suggest Fault-Masking Terms (MATEs) to effectively prune the fault space for gate-level fault injection campaigns by using the (software-induced) hardware state to dynamically cut off benign faults. Our tool applied to an AVR core and a size-optimized MSP430 implementation shows that up to 21 percent of all SEUs on flip-flop level are masked within one clock cycle.

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  1. Cross-layer fault-space pruning for hardware-assisted fault injection

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    • Published in

      cover image ACM Conferences
      DAC '18: Proceedings of the 55th Annual Design Automation Conference
      June 2018
      1089 pages
      ISBN:9781450357005
      DOI:10.1145/3195970

      Copyright © 2018 ACM

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      Publication History

      • Published: 24 June 2018

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