Soheil Hashemi
ABSTRACT
Approximate computing is an emerging paradigm where design accuracy can be traded off for benefits in design metrics such as design area, power consumption or circuit complexity. In this work, we present a novel paradigm to synthesize approximate circuits using Boolean matrix factorization (BMF). In our methodology the truth table of a sub-circuit of the design is approximated using BMF to a controllable approximation degree, and the results of the factorization are used to synthesize a less complex subcircuit. To scale our technique to large circuits, we devise a circuit decomposition method and a subcircuit design-space exploration technique to identify the best order for subcircuit approximations. Our method leads to a smooth trade-off between accuracy and full circuit complexity as measured by design area and power consumption. Using an industrial strength design flow, we extensively evaluate our methodology on a number of testcases, where we demonstrate that the proposed methodology can achieve up to 63% in power savings, while introducing an average relative error of 5%. We also compare our work to previous works in Boolean circuit synthesis and demonstrate significant improvements in design metrics for same accuracy targets.
- Jason Cong and Yuzheng Ding. 1994. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 13 (1994), 1--12. Google Scholar
Digital Library
- Soheil Hashemi, R. Iris Bahar, and Sherief Reda. 2015. DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '15). IEEE Press, Piscataway, NJ, USA, 418--425. Google ScholarDigital Library
- Mohsen Imani, Daniel Peroni, and Tajana Rosing. 2017. CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing. In Proceedings of the 54th Annual Design Automation Conference 2017 (DAC '17). ACM, New York, NY, USA, Article 76, 6 pages. Google ScholarDigital Library
- A. B. Kahng and S. Kang. 2012. Accuracy-configurable adder for approximate arithmetic designs. In DAC Design Automation Conference 2012. 820--825. Google ScholarDigital Library
- D. D. Lee and H. S. Seung. 1999. Learning the Parts of Objects by non-negative matrix factorization. Nature 401 (1999), 788--791.Google ScholarCross Ref
- S. Lee, L. K. John, and A. Gerstaluer. 2017. High-Level Synthesis of Approximate Hardware under Joint Precision and Voltage Scaling. In Design, Automation and Test in Europe. Google ScholarDigital Library
- C. Li, W. Luo, Sachin S. Sapatnekar, and Jiang Hu. 2015. Joint precision optimization and high level synthesis for approximate computing. In Design Automation Conference. 104:1--6. Google ScholarDigital Library
- Osvaldo Martinello, Renato Perez Ribas Felipe Marque, and Andr?? Reis. 2010. KL-Cuts: A New Approach for Logic Synthesis Targeting Multiple Output Blocks. In Design Automation Test in Europe. 777--782. Google ScholarDigital Library
- Jin Miao, Andreas Gerstlauer, and Michael Orshansky. 2013. Approximate Logic Synthesis Under General Error Magnitude and Frequency Constraints. In Proceedings of the International Conference on Computer-Aided Design. 779--786. Google ScholarDigital Library
- P. Miettinen and J. Vreeken. 2011. Model order selection for boolean matrix factorization. In Proceedings of the 17th ACM SIGKDD international conference on Knowledge discovery and data mining. 51--59. Google ScholarDigital Library
- P. Miettinen and J. Vreeken. 2014. MDL4BMF: Minimum Description Length for Boolean Matrix Factorization. ACM Transactions on Knowledge Discovery from Data 8, 4 (2014), 18:1--31. Google ScholarDigital Library
- K. Nepal, S. Hashemi, C. Tann, R. I. Bahar, and S. Reda. 2016. Automated High-Level Generation of Low-Power Approximate Computing Circuits. In IEEE Transactions on Emerging Topics in Computing.Google Scholar
- K. Nepal, Y. Li, R. I. Bahar, and S. Reda. 2014. "ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits. In Design, Automation and Test in Europe. 1--6. Google ScholarDigital Library
- Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, and Anand Raghunathan. 2014. ASLAN: Synthesis of Approximate Sequential Circuits. In Design, Automation & Test in Europe Conference. 1--6. Google ScholarDigital Library
- Semeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar, and Jürg Henkel. 2016. Architectural-space Exploration of Approximate Multipliers. In Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD '16). ACM, New York, NY, USA, Article 80, 8 pages. Google ScholarDigital Library
- Zdenek Vasicek and Lukas Sekanina. 2016. Evolutionary design of complex approximate combinational circuits. Genetic Programming and Evolvable Machines 17, 2 (01 Jun 2016), 169--192. Google ScholarDigital Library
- Swagath Venkataramani, Kaushik Roy, and Anand Raghunathan. 2013. Substitute-and-simplify: A Unified Design Paradigm for Approximate and Quality Configurable Circuits. In Design, Automation and Test in Europe. 1367--1372. Google ScholarDigital Library
- S. Venkataramani, A. Sabne, V. Kozhikkottu, K. Roy, and A. Raghunathan. 2012. SALSA: Systematic logic synthesis of approximate circuits. In DAC Design Automation Conference 2012. 796--801. Google ScholarDigital Library
- C. Wolf. {n. d.}. Yosys Open Synthesis Suit. http://www.clifford.at/yosys/.Google Scholar
- W. Xu, X. Liu, and Y. Gong. 2003. Document clustering based on non-negative matrix factorization. In ACM SIGIR conference on Research and development in information retrieval. 267--273. Google ScholarDigital Library
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