Using a single input to support multiple scan chains

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Using a single input to support multiple scan chains

Full text

Pdf (507 KB)

Source

International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 74 - 78

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Kuen-Jong Lee	Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C.
Jih-Jeen Chen	Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C.
Cheng-Hua Huang	Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C.

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 19, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTex EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/288548.288563 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Scott Fetherston , Imtiaz P. Shaik , Siyad C. Ma, Testability Features of AMD-K6TM Microprocessor, Proceedings of the IEEE International Test Conference, p.406-413, November 03-05, 1997
	2	Zaifu Zhang , Robert D. McLeod, An Efficient Multiple Scan Chain Testing Scheme, Proceedings of the 6th Great Lakes Symposium on VLSI, p.294, March 22-23, 1996
	3	S. Narayanan , M. A. Breuer, Asynchronous multiple scan chains, Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), p.270, April 30-May 03, 1995
	4	S. lee and K.G. Shin, "Design for Test Using Partial Parallel scan" IEEE Trans. on Computers. 1990, pp.203-211
	5	"IEEE Standard 11"49.1-1990. IEEE Standard Test Access Port and Boundary Scan Architecture." IEEE Standard Board, New York, N.Y., 1990.
	6	P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuit," IEEE Trans. on Computers, Vol C-30, No.3, pp.215-222, March, 1981.
	7	P. Goel and B.C. Rosales, "Test Generation & Dynamic Compaction of tests," in digest of Test Conference, pp.189-192, Oct. 1979.
	8	M. Abramovici and J.J. Kulikowski, "Smart and Fast: Test generation for VLSI scan-design circuits," IEEE Design and Test of Computers, pp.43-54, Aug. 1986.
	9	J.S. Chang and C.S. Lin, "Test Set Compaction for Combinational Circuits" IEEE Trans. on Computers, Nov, 1995, pp.1370-1378.
	10	B. Krishnamurthy and S.B. Akers, "On the complexity of estimating the size of a test set" IEEE Trans. on Computers, Aug. 1984, pp.750-753.
	11	P.H. Bardell and W.H. McAnney, "Self-Testing of Multichip Logic Modules," Proc. lntn'l. Test Conf., Nov, 1982, pp.200-204.
	12	Hyung Ki Lee , Dong Sam Ha, An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.946-955, October 26-30, 1991
	13	E.J. McCluskey, "Verification Testing- A Pseudoexhaustive Test Technique," IEEE Trans. on Computers, Vol. C-33, No. 6, June, 1984, pp.541-546.

CITED BY 8

	Nahmsuk Oh , Rohit Kapur , T. W. Williams , Jim Sproch, Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture, Proceedings of the conference on Design, Automation and Test in Europe, p.10110, March 03-07, 2003
	Dong Xiang , Shan Gu , Jia-Guang Sun , Yu-liang Wu, A cost-effective scan architecture for scan testing with non-scan test power and test application cost, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Sying-Jyan Wang , Sheng-Nan Chiou, Generating efficient tests for continuous scan, Proceedings of the 38th conference on Design automation, p.162-165, June 2001, Las Vegas, Nevada, United States
	Quming Zhou , Kedarnath J. Balakrishnan, Test cost reduction for SoC using a combined approach to test data compression and test scheduling, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Carl Barnhart , Vanessa Brunkhorst , Frank Distler , Owen Farnsworth , Andrew Ferko , Brion Keller , David Scott , Bernd Koenemann , Takeshi Onodera, Extending OPMISR beyond 10x Scan Test Efficiency, IEEE Design & Test, v.19 n.5, p.65-72, September 2002
	Gang Zeng , Hideo Ito, Concurrent core test for SOC using shared test set and scan chain disable, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Youhua Shi , Nozomu Togawa , Shinji Kimura , Masao Yanagisawa , Tatsuo Ohtsuki, FCSCAN: an efficient multiscan-based test compression technique for test cost reduction, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Xiao Liu , Michael S. Hsiao , Sreejit Chakravarty , Paul J. Thadikaran, Efficient techniques for transition testing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.258-278, April 2005