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Soft decision maximum likelihood decoders for binary linear block codes implemented on FPGAs (abstract)
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays table of contents
Monterey, California, United States
Page: 261  
Year of Publication: 1998
ISBN:0-89791-978-5
Authors
Hidehisa Nagano
Takayuki Suyama
Akira Nagoya
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
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Additional Information:

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DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/275107.275166
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
  B.8 Performance and Reliability


General Terms:
Design, Experimentation, Performance

Collaborative Colleagues:
Hidehisa Nagano: colleagues
Takayuki Suyama: colleagues
Akira Nagoya: colleagues

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