Ming-Chang Yang
Tei-Wei Kuo
ABSTRACT
The market trend of flash memory chips has been going for high density but low reliability. The rapidly increasing bit error rates and emerging reliability issues of the coming triple-level cell (TLC) and even three-dimensional (3D) flash chips would let users take an extremely high risk to store data in such low reliability storage media. With the observations in mind, this paper rethinks the layer design of flash devices and propose a complete paradigm shift to re-configure physical flash chips of potentially massive parallelism into better "virtual chips", in order to improve the data recoverability in a modular and low-cost way. The concept of virtual chips is realized at hardware abstraction layer (HAL) without continually complicating the conventional flash management software (i.e., flash translation layer (FTL)). The capability and compatibility of the proposed design are then verified by a series of experiments with encouraging results.
- Flash-memory Translation Layer for NAND flash (NFTL). M-Systems, 1998.Google Scholar
- Amir Ban. Flash File System. US Patent 5,404,485. In M-Systems, April 1995.Google Scholar
- Yuan-Hao Chang, Jen-Wei Hsieh, and Tei-Wei Kuo. Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design. In DAC, June 2007. Google ScholarDigital Library
- Yuan-Hao Chang and Tei-Wei Kuo. A Commitment-based Management Strategy for the Performance and Reliability Enhancement of Flash-memory Storage Systems. In DAC, 2009. Google ScholarDigital Library
- Bill Dawkins and Arnold Jones. Common RAID Disk Data Format Specification. Technical report, SNIA Technical Position, August 2007.Google Scholar
- Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, and Jack K. Wolf. Characterizing Flash Memory: Anomalies, Observations, and Applications. In MICRO, 2009. Google ScholarDigital Library
- Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. In ASPLOS, 2009. Google ScholarDigital Library
- Yang Hu, Hong Jiang, Dan Feng, Lei Tian, Hao Luo, and Chao Ren. Exploring and exploiting the multilevel parallelism inside ssds for improved performance and endurance. IEEE Transactions on Computers, 62(6):1141--1155, 2013. Google ScholarDigital Library
- Soojun Im and Dongkun Shin. Flash-Aware RAID Techniques for Dependable and High-Performance Flash Memory SSD. IEEE Transactions on Computers, 60(1), 2011. Google ScholarDigital Library
- Jesung Kim, Jong Min Kim, Sam H. Noh, Sang Lyul Min, and Yookun Cho. A Space-Efficient Flash Translation Layer For CompactFlash Systems. IEEE Transactions on Consumer Electronics, Nov 2002. Google ScholarDigital Library
- S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song. A log buffer-based flash translation layer using fully-associative sector translation. ACM Transactions on Embedded Computing Systems, 6(3), July 2007. Google ScholarDigital Library
- SNIA. IOTTA repository. http://iotta.snia.org/tracetypes/3.Google Scholar
- Neal Mielke, Todd Marquart, Ning Wu, Jeff Kessenich, Hanmant Belgal, Eric Schares, Falgun Trivedi, Evan Goodness, and Leland R. Nevill. Bit Error Rate in NAND Flash Memories. In IRPS, 2008.Google Scholar
- Muthukumar Murugan and David. H. C. Du. Rejuvenator: A static wear leveling algorithm for nand flash memory with minimized overhead. In MSST, 2011. Google ScholarDigital Library
- Yi Qin, Dan Feng, Jingning Liu, Wei Tong, Yang Hu, and Zhiming Zhu. A Parity Scheme to Enhance Reliability for SSDs. In NAS, June 2012. Google ScholarDigital Library
- Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao, and Yong Guan. Mnftl: An efficient flash translation layer for mlc nand flash memory storage systems. In DAC, 2011. Google ScholarDigital Library
- Avishay Traeger, Erez Zadok, Nikolai Joukov, and Charles P. Wright. A Nine Year Study of File System and Storage Benchmarking. Trans. Storage, 4:5:1--5:56, May 2008. Google ScholarDigital Library
- Yi Wang, Zili Shao, H. C. B. Chan, L. A. D. Bathen, and N. D. Dutt. A reliability enhanced address mapping strategy for three-dimensional (3-d) nand flash memory. IEEE Transactions on VLSI Systems, 22(11):2402--2410, Nov 2014.Google ScholarCross Ref
Index Terms
- Virtual flash chips: rethinking the layer design of flash devices to improve data recoverability
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