ABSTRACT
Over the past decade, digital signal processors (DSPs) have emerged as the processors of choice for implementing embedded applications in high-volume consumer products. Through their use of specialized hardware features and small chip areas, DSPs provide the high performance necessary for embedded applications at the low costs demanded by the high-volume consumer market. One feature commonly found in DSPs is the use of dual data-memory banks to double the memory system's bandwidth. When coupled with high-order data interleaving, dual memory banks provide the same bandwidth as more costly memory organizations such as a dual-ported memory. However, making effective use of dual memory banks remains difficult, especially for high-level language (HLL) DSP compilers.In this paper, we describe two algorithms --- compaction-based (CB) data partitioning and partial data duplication --- that we developed as part of our research into the effective exploitation of dual data-memory banks in HLL DSP compilers. We show that CB partitioning is an effective technique for exploiting dual data-memory banks, and that partial data duplication can augment CB partitioning in improving execution performance. Our results show that CB partitioning improves the performance of our kernel benchmarks by 13%-40% and the performance of our application benchmarks by 3%-15%. For one of the application benchmarks, partial data duplication boosts performance from 3% to 34%.
- 1.Gianluigi Castelli, Guest Editor's Introduction: 'Whe Seemingly Unlimited Market for Microcontroller-Based Embedded Systems," IEEE Micro, Vol. 15, No. 5, pp. 6-8, October, 1995. Google ScholarDigital Library
- 2.Bennett Z. Kobb, "Telecommunications," IEEE Spectrum, pp. 30-34, January, 1995. Google ScholarDigital Library
- 3.Edward A. Lee, "Programmable DSP Architectures," IEEE ASSP Magazine, Part I: pp.4-19, October, 1988; Part iI: pp. 4-14, January, 1989.Google ScholarCross Ref
- 4.Mazen A. R. Saghir, Paul Chow, and Corinna G. Lee, ''Towards Better DSP Architectures and Compilers," Proceedings of the International Conference on Signal Processing Applications and Technology, pp. 658-664, DSP Associates, October, 1994.Google Scholar
- 5.Ruby B. Lee, "Accelerating Multimedia with Enhanced Microprocessors," IEEE Micro, Vol. 15, No. 2, pp. 22-32, April, 1995. Google ScholarDigital Library
- 6.L. Kohn, G. Maturana, M. Tremblay, A. Prabhu, G. Zyner, "The Visual Instruction Set (VIS) in UltraSPARC," Proceedings of Compcon '95, pp. 462-469, March, 1995. Google ScholarDigital Library
- 7.Upcoming issue of IEEE Micro on Media Processing, August, 1996.Google Scholar
- 8.Recent IC Announcements, Microprocessor Report, p. 27, August 21, 1995.Google Scholar
- 9.Most Significant Bits, Microprocessor Report, pp. 4-5, July 31, 1995.Google Scholar
- 10.John Hennessy and David Patterson, Computer Architecture: A Quantitative Approach, Second Edition, Morgan Kaufmann Publishers, Inc., 1995. Google ScholarDigital Library
- 11.Linley Gwennap, "Improved Cost Model Puts Pentium at $180," Microprocessor Report, pp. 14-15, September 12, 1994.Google Scholar
- 12.Jim Turley and Phil Lapsley, "New 56301 DSP Doubles 24-Bit Performance," Microprocessor Report, pp. 14-15, December 4, 1995.Google Scholar
- 13.Jose Luis Pino, Soonhoi Ha, Edward A. Lee, and Joseph T. Buck, "Software Synthesis for DSP Using Ptolemy," Journal of VLSI Signal Processing,. Vol. 9, No. 1-2, pp. 7-21, January, 1995. Google ScholarDigital Library
- 14.Vojin Zivojnovic, Harald Schraut, M. Willems, and R. Schoenen, "DSPs, GPPs, and Multimedia Applications - An Evaluation Using DSPstone," Proceedings of the International Conference on Signal Processing Applications and Technology, pp. 1779-1783, DSP Associates, October, 1995.Google Scholar
- 15.Alfred V. Aho, Ravi Sethi, and Jeffrey D. Ullman, Compilers: Principles, Techniques, and Tools, Addison-Wesley Publishing Company, 1986. Google ScholarDigital Library
- 16."MIPS Open RISC Technology R10000 Microprocessor Technical Brief', http: //www.mips. com/rl0k/ r10000_Pr_Info/R10000_Tech_Br_cv. html, October, 1994.Google Scholar
- 17.DSP56000/DSP56001 Digital Signal Processor User's Manual, Motorola, 1990.Google Scholar
- 18.Monica S. Lam, "Software Pipelining: An Effective Scheduling Technique for VLiW Machines," SIGPIAN Conference on Programming Language Design and Implementation, pp. 318-328, ACM, June, 1988. Google ScholarDigital Library
- 19.Carla Procaskey, "Improving Compiled DSP Code Through Language Extensions," Proceedings of the International Conference on Signal Processing Applications and Technology, pp. 846-850, DSP Associates, October, 1995.Google Scholar
- 20.Ashok Sudarsanam and Sharad Malik, "Memory Bank and Register Allocation in Software Synthesis for ASIPS," Proceedings of the International Conference on Computer- Aided Design, pp. 388-392, IEEE/ACM, 1995. Google ScholarDigital Library
- 21.P.G. Lowney, et. al., 'Whe Multifiow Trace Scheduling Compiler," Journal of Supercomputing, Vol. 7, Issue I-2, pp. 51-142, May, 1993. Google ScholarDigital Library
- 22."SUIF: An Infrastructure for Research on Parallelizing and Optimizing Compilers," http://suif, stanford. edu/suif / sui f-overview/suif, html, 1994.Google Scholar
- 23.Joseph Fisher, "Very Long Instruction Word Architectures and the ELI-512," Proceedings of the l Oth International Symposium on Computer Architecture, pp. 140-150, IEEE, 1983. Google ScholarDigital Library
- 24.Richard M. Stallman, Using and Porting GNU C, Free Software Foundation, Inc., 1990.Google Scholar
- 25.David Landskov, Scott Davidson, Bruce Shriver, and Patrick W. Mallett, "Local Microcode Compaction Techniques,'' Computing Surveys, 12(3): pp. 261-294, ACM, September, 1980. Google ScholarDigital Library
- 26.Michael R. Garey and David S. Johnson, Computers and Intractability: A Guide to the Theory of NP. Completeness, W. H. Freeman and Company, 1979. Google ScholarDigital Library
- 27.Mazen A. R. Saghir, Paul Chow, and Corinna G. Lee, "Application-Driven Design of DSP Architectures and Compilers," Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, pp. II-437- 440, IEEE, 1994.Google Scholar
Index Terms
- Exploiting dual data-memory banks in digital signal processors
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